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A three-value adiabatic d flip-flop and four-digit three-value adiabatic synchronous reversible counter

A flip-flop, adiabatic technology, applied in the direction of synchronous pulse counters, etc., can solve the problems of increasing the chip area and reducing the packaging density of integrated circuits

Inactive Publication Date: 2011-12-21
HANGZHOU MAEN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the adiabatic circuit breaks through the limitations of the energy transmission mode in the traditional CMOS circuit and effectively reduces the power consumption of the circuit, it increases the chip area to some extent and reduces the packaging density of the integrated circuit.

Method used

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  • A three-value adiabatic d flip-flop and four-digit three-value adiabatic synchronous reversible counter
  • A three-value adiabatic d flip-flop and four-digit three-value adiabatic synchronous reversible counter
  • A three-value adiabatic d flip-flop and four-digit three-value adiabatic synchronous reversible counter

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Experimental program
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Effect test

Embodiment 1

[0035] Embodiment 1: According to the logical relationship to be realized by the circuit, the truth table of the three-valued adiabatic D flip-flop with reset and set terminals can be obtained, as shown in Table 1.

[0036] Table 1 The truth table of the three-valued adiabatic D flip-flop with reset and set terminals

[0037]

[0038]The present invention combines "Design of a DTCTGAL circuit and its application" disclosed in the Chinese Journal of Semiconductors on the basis of analyzing the truth table of Table 1 (authors: Wang Pengjun, Li Kunpeng, and Mei Fengna) [Journal of Semiconductors, "Based on DTCTGAL circuit design and application of dual-power clock", Wang Pengjun, Li Kunpeng, Mei Fengna], design a three-valued adiabatic D flip-flop: first use the clock to control the clock The controlled NMOS tube is used for the reset signal R, the set signal S, the input signal D, and the complementary reset signal complementary set signal and complementary input signals...

Embodiment 2

[0043] Embodiment 2: Since the three-value adiabatic D flip-flop only has the function of memorizing three-value data, and does not have the function of directly counting three values ​​of input pulses, the synchronous reversible counter should also have the function of counting down. From the definition of anti-circulation operator in Post algebra, it can be seen that anti-circulation gate has a decrement function.

[0044] x ← =(X-1) mod 3

[0045] Among them, X, X ← are the input and output of the reverse loop gate, respectively. According to the logical relationship to be realized by the circuit, the truth table of the three-valued adiabatic reverse cycle gate can be obtained, as shown in Table 2, where in, is the complementary input signal, out, are complementary output signals.

[0046] Table 2 The truth table of the three-valued anti-circulation gate

[0047]

[0048] On the basis of analyzing Table 2, combine the "Design of a DTCTGAL circuit and its applicat...

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Abstract

The invention discloses a ternary heat insulation D trigger and a four-bit ternary heat insulation synchronous reversible counter, wherein the ternary heat insulation D trigger realizes corresponding circuits by taking the three elements theory of the circuit as guidance, combining with the three elements theory of the circuit and utilizing an NMOS (N-mental-oxide-semiconductor) transistor and a cross storage type structure with different threshold values; and the four-bit ternary heat insulation synchronous reversible counter realizes processing of a ternary signal by introducing the energy recovery theory of the heat insulation circuit, being based on the design principal of the a synchronous counter, coordinately using the ternary heat insulation D trigger, a ternary heat insulation reverse circulation gate, a ternary heat insulation reverse circulation circuit with a borrow function and a ternary heat insulation one-out-of-two data selector, adopting a two-phase power clock and utilizing a bootstrapping operated MOS (metal-oxide semiconductor) pipe with different threshold values to finish injecting and recovering the energy output by the circuit. The ternary heat insulation D trigger and the four-bit ternary heat insulation synchronous reversible counter have the advantages that the connection lines between the circuits are reduced, the chip area is saved, the packaging intensity of the integrated circuit is increased, the circuit power consumption is effectively reduced, and the average power consumption can be reduced to 67.5% compared with the traditional CMOS (complementary metal-oxide-semiconductor) synchronous reversible counter.

Description

technical field [0001] The invention relates to a D flip-flop, in particular to a three-value adiabatic D flip-flop and a four-digit three-value adiabatic synchronous reversible counter. Background technique [0002] In the VLSI of the existing deep submicron process, low power consumption and high packaging density have become important goals considered in chip design, and the research on low power consumption and high packaging density technology has become more and more important in integrated circuit design. field. A counter is an important functional device that constitutes a digital system. It can not only be used to count clock pulses, but also be used for frequency division, timing, generation of beat pulses and pulse sequences, and digital operations. Most of the traditional counters are powered by DC power supply, and its energy is always consumed at one time by power supply→capacitor→ground. While reducing power supply voltage and node capacitance can be used to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/52
Inventor 汪鹏君梅凤娜
Owner HANGZHOU MAEN TECH
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