30 results about "Dark count rate" patented technology

A solid-state photomultiplier (SSPM) includes an optical isolation structure therein. The SSPM includes a substrate and an epitaxial diode layer positioned on the substrate. A plurality of avalanche photodiodes (APDs) are fabricated on the epitaxial diode layer and the optical isolation structure is positioned about the plurality of APDs to separate each of the plurality of APDs from adjacent APDs. The optical isolation structure contains at least one of a light absorbing material and a light reflecting material deposited therein to reduce optical crosstalk and dark count rate in the SSPM.

Avalanche photodiodes are provided, wherein the APDs provide both high optical coupling efficiency and low dark count rate. The APDs are formed such that their cap layer has an active region of sufficient width to enable high optical coupling efficiency but the APD still exhibits a low dark count rate. These cap layers have a device area with an active region and an edge region, wherein the size of the active region is substantially matched to the mode-field diameter of an optical beam, and wherein the size of the edge region is made small so as to reduce the number of defects included. These APD designs maintain a substantially uniform gain and breakdown voltage, as necessary for practical use.

The invention discloses a single-photon avalanche diode detector array unit with high detection efficiency. The array unit is a SPAD structure with surrounding P-injection, P-buried layer and deep P-well protected by P-buried layer. A deep P well is formed by ion implantation in the deep P well. There are two buried layer regions in the deep P well, namely the P buried layer region 3 and the P-buried layer region 4. There is a P-implanted region above the P-buried layer region 4. 8 surround. The array unit structure can effectively improve the photon detection efficiency of the SPAD device, and the dark count rate is very low, which greatly improves the overall performance of the SPAD detector.

The SPAD device comprises a single-photon avalanche diode and a further single-photon avalanche diode having breakdown voltages, the single-photon avalanche diodes being integrated in the same device. The breakdown voltages are equal or differ by less than 10%. The single-photon avalanche diode is configured to enable to induce triggering or to have a dark count rate that is higher than the dark count rate of the further single-photon avalanche diode.

The invention discloses a single-photon avalanche photoelectric diode detector structure which comprises a P-type silicon substrate, a deep N well and a deep P well, wherein the deep N well and the deep P well are formed in the P-type silicon substrate; an N<+> zone and a P<+> zone for forming a multiplication zone for absorbing photons are formed in the deep N well; a first P well zone and an N well zone for forming an avalanche photoelectric diode structure are formed around the multiplication zone; an anode lead-out end is formed in the N well zone; a cathode lead-out end is formed in the P<+> zone; a second P well zone is formed in the deep P well; a substrate lead-out end is formed in the second P well zone; the surfaces of the deep N well and the deep P well are covered by protectionlayers. The single-photon avalanche photoelectric diode detector structure is simple in structure, only two PN junctions are formed in a vertical direction of a junction depth, a PN junction isolation mode is adopted in a whole unit structure, dark count rates caused by defects of STI can be completely eliminated, the unit area can be greatly reduced, and the filling rate can be increased. The invention further discloses a producing method of the single-photon avalanche photoelectric diode detector structure.

The invention provides a low-dark-count-rate CMOS SPAD photoelectric device. A P-well layer is added based on a routine P+ / N-well type SPAD structure. The P-well layer is arranged between the P+ layerand the N-well layer. Furthermore, an N-well clearance is utilized as a virtual protecting ring of the structure; namely N-wells are added at two sides of a PN junction, wherein the structure is shown in the attached figures of an abstract. An incident photon is incident into the device and is attracted at the central N well, and furthermore a photon-generated carrier is generated. The P-well layer and the N-well layer are utilized at two sides of the PN junction. Hereon an avalanche junction is a P-well / N-well junction. Because the avalanche junction is a lightly doped avalanche junction, width of a depletion region increases, and probability of interband tunneling of the carries is reduced, thereby reducing the dark counting rate. Furthermore the virtual protecting ring is used for suppressing edge breakdown of the PN junction. The forming principle of virtual protection is characterized in that transverse diffusion exists between adjacent N-wells and therefore the N- virtual protecting ring is formed at the PN junction. The low-dark-count-rate CMOS SPAD photoelectric device is designed at two aspects of the protecting ring and the depletion region width, dark current of the device is reduced, thereby reducing the dark count rate.