276 results about "12-bit" patented technology

An apparatus, system and method can be arranged for coding and / or decoding with a phase invariant coding scheme that is useful for short burst signaling devices. 10-bit data is mapped into a 12-bit data with a non-coherent burst code mapper. A parity generator creates a 12-bit parity data to form a 24-bit extended binary Golay code from the 12-bit data. The values for selected bit fields in the 12-bit data and 12-bit parity data are swapped to generate I and Q data such that sensitivity to changes in rotational phase is removed. I and Q data can be used by a transmitter to transmit a rotationally-invariant signal. On receipt, I and Q signals can be recovered, reverse swapped to generate the parity and data signals, and remapped to recover the transmitted 10-bit data. The receiver can also be arranged to use a soft decoding method for improved signal integrity.

This invention provides a paging method for Multimedia Broadcast / Multicast Service in mobile communication system paging process and radio resource setup process are merged in this method to try to reduce uplink responses. This invention extends existing PCH IubFP frame structure by adding MBMS Indication bit(MI) to PCH IubFP frame. The PCH IubFP frame includes Paging Indication (PI) and Paging Message. Paging message carries MBMS service information. MBMS Service Identity or MBMS Paging Indicator is added to the reserved 12 bits in Paging Indicator Channel (PICH) frame structure. Radio Network Controller (RNC) transfers Paging Indicator Message and paging message to Base Station (Node B) so as to send over the air-interface.

An embedded additional user interface 10 includes a web page display screen 20 and an embedded processor 30, and is incorporated into a gaming machine 40 that in turn includes a gaming screen 50 and a gaming processor 60. The embedded processor 30 employs an internal operating system and communicates with the gaming processor 60. The embedded processor reads incoming data, translates the data into a web authoring language, and maps the data to the web page display screen. The display screen 20 presents web page information to a user via the display screen, thereby increasing user excitement by providing a richer gaming experience. This provides a dramatic improvement over traditional system components 70 (input / output peripherals) that have been used in the past to access service and system information, such as a 2-line, 20-character VF display and a 12-digit keypad.

The invention presents a scalable solution to encode the whole 12-bit raw video once to generate one bitstream that contains an H.264 / AVC compatible base layer and a scalable enhancement layer. If a color bit depth scalable decoder is available at the client end, both the base layer and the enhancement layer sub-bitstreams will be decoded to obtain the 12-bit video and it can be viewed on a high quality display that supports more than eight bit; otherwise only the base layer sub-bitstream is decoded using an H.264 / AVC decoder and the decoded 8-bit video can be viewed on a conventional 8-bit display. The enhancement layer contains a residual based on a prediction from the base layer, which is either based on bit-shift or based on an advanced bit depth prediction is utilized, wherein the advanced bit depth prediction method is a Smoothed Histogram method or a Localized Polynomial Approximation method.

The invention relates to a water environment monitoring node based on ZigBee wireless technique. The prior technology has long monitoring period and large work intensity, and cannot reflect dynamic variation of water environment. The invention includes an electric power management module, a water quality parameter acquisition module, an MPU module and a ZigBee radio frequency module. The equipment adopts an MSP430F149 MPU, for analyzing and processing water environmental parameter, and controls the operating status of the ZigBee radio frequency module and the water quality parameter acquisition module. The MSP430F149 processor is interconnected to the water quality parameter acquisition module through a 12 bit A / D converter self integrated with the MSP430F149 processor, and is interconnected to the ZigBee radio frequency module through an SPI serial interface, meanwhile also controls a power supply management module to supply power through an analogue switch, so as to achieve the goal of energy-saving. The invention has low cost, and low power consumption; can be arranged in water environment for a long term, execute multiple parameter real time monitoring to the water environment, and complete the high-efficiency transmission of data, thereby having wide applications prospect in the water environment monitoring.

A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit / receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ΣΔ A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

This invention provides a paging method for Multimedia Broadcast / Multicast Service in mobile communication system. The paging process and radio resource setup process are merged in this method to try to reduce uplink responses. This invention extends existing PCH IubFP frame structure by adding MBMS Indication bit(MI) to PCH IubFP frame. The PCH IubFP frame includes Paging Indication (PI) and Paging Message. Paging message carries MBMS service information. MBMS Service Identity or MBMS Paging Indicator is added to the reserved 12 bits in Paging Indicator Channel (PICH) frame structure. Radio Network Controller (RNC) transfers Paging Indicator Message and paging message to Base Station (Node B) so as to send over the air-interface.

The invention belongs to the technical field of an integrated circuit, and particularly relates to a reconfigurable continuous time type high-speed low-power consumption sigma-delta modulator. The reconfigurable continuous time type high-speed low-power consumption sigma-delta modulator is formed by a configurable loop filter, a multi-digit quantizer and a feedback ADC (Analog to Digital Converter). According to a circuit structure, the loop filter adopts a third-order active RC (Remote Control) filter structure, the multi-digit quantizer is realized by adopting an interpolating method, and the feedback ADC adopts a high-speed dynamic element matching technology. According to the reconfigurable continuous time type high-speed low-power consumption sigma-delta modulator disclosed by the invention, under different bandwidth modes, the modulator can be switched between a distribution feedforward structure with a harmonic oscillator and a distribution feedback structure with a harmonic oscillator, and the optimization for the accuracy and the energy efficiency in various bandwidth areas can be realized in system level; continuous analog signal inputs can be converted into discrete digital signal outputs by the modulator in 1.2V power supply voltage, signal bandwidths can be configured in four modes of 5MHz, 10MHz, 15MHz and 20MHz, the accuracy can be up to 11-12 bits, and each frequency range of a wireless communication protocol LTE (Long Term Evolution) can be covered.

The invention discloses a digital calibration system of partial discharge test equipment. The digital calibration system is characterized in that the system comprises a device to be tested, and a digital calibrator and a measurement and control computer of the partial discharge test equipment which is connected with the device to be tested, wherein the output end of the digital calibrator of the partial discharge test equipment is connected with the measurement and control computer; the measurement and control computer compares the collected waveform and data measured value with the standard value output by the digital calibrator to perform analysis and calculation and obtain the error of the measured value and the standard value, outputs the error value, and measured value and standard value to a data outputting machine so as to realize the calibration of the partial discharge test equipment. In the system of the invention, the wide measuring range which is 1-10000pc, the high accuracy standard pulse calibrator and a high speed data acquisition card with 12 bits of precision are adopted to ensure the calibration accuracy to reach + / -2%.

The invention relates to a multi-single-phase / three-phase alternating current voltage stabilizer based on digital circuit control. The voltage stabilizer comprises: an input terminal is connected with three compensation transformers of a power grid, an output terminal is connected to an input terminal of electrical equipment via series connection of primary windings of the three transformers, and secondary winding terminals of the three transformers are connected to an output voltage terminal via 8 bidirectional thyristors, a TR4 transformer at an input voltage side provides real-time voltage detection signals, alternating current effective value detection is conducted via a 12-bit high-precision A / D converter, single-phase alternating current work voltage is monitored in real time, obtained high 9-bit digital signals and a set coding amount value are compared, the 8 bidirectional thyristors are determined, combined, and triggered via a decoding driving circuit according to a hardware logic programming regulation, the employed group number of secondary windings of the transformers and the voltage direction are changed via different combinations of turn-on and turn-off of the bidirectional thyristors, different compensation combinations for measuring the voltage at one step are finally achieved, and the output voltage is guaranteed to be stabilized in a given voltage range.

In a video processing system, a method and system for dynamically configurable DCT / IDCT module in a wireless handset are provided. A processor may be used to configure a quantization scheme and video format mode of operation and to configure a processing network in a DCT / IDCT module. The mode of operation may depend on whether the received video signal is in JPEG, MPEG, and / or H.263 format. The processing network may be configured into a DCT processing network configuration or an IDCT processing network configuration based on whether the received video signal is to be encoded or decoded respectively. The DCT / IDCT module may comprise a FIFO, an adder / subtractor, a multipler / accumulator, a plurality of digital dividers, and a de-quantizer. The plurality of digital dividers may comprise a 12-bit divider and an 7-bit divider. The mode and configuration modifications may be dynamically performed during operation of the wireless handset.

A judging unit compares data in a dither table for each display pixel with a numerical value of low-order 2 bits of an input signal (12 bits) and outputs 1 to an adder when the numerical value of the low-order 2 bits of the input signal is larger than the data in the dither table, while outputting 0 to the adder in other cases. The adder adds the value outputted from the judging unit to an uneven luminance correction value read from a correction memory, so that the uneven luminance correction value is corrected. A multiplier multiplies the input signal by the uneven luminance correction value after the correction.

An integrated color interpolation and color space conversion technique and apparatus. A raw image that is arranged in a Bayer pattern where each pixel has only one of the color components needed to form a full color resolution pixel may be converted using this technique directly to a YCrCb image space without any intermediate conversion or interpolation steps. Specifically, in one instance, an 8-bit Bayer pattern raw image may be converted directly to a 12-bit YCrCb space in a single step approach. Such an integrated technique may more readily and inexpensively implemented in hardware such as on a digital camera, or in software.

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For ⅓ rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For ¼ rate, the LDPC code has the following relevant parameters: q=135, nldpc=64,800, kldpc=nBCH=16200, kBCH=16008 (12 bit error correcting BCH). For ⅖ rate, the following parameters exist: q=108, nldpc=64800, kldpc=nBCH=25920, kBCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.