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40results about How to "Stress" patented technology

Panel of organic electroluminescent display

An organic electroluminescent display panel comprises a substrate, at least one organic light-emitting area, at least one protecting layer, at least one isolation layer and at least one protrusion. In this case, the organic light-emitting area comprises a plurality of pixels and is disposed over the substrate. The protecting layer is disposed over the substrate and the organic light-emitting area. The isolation layer is disposed over the protecting layer.
Owner:RITDISPLAY

Preparation of photomask blank and photomask

ActiveUS20050260505A1Improve chemical resistanceSuppress changesCellsVacuum evaporation coatingFlash-lampResist
A photomask blank is prepared by forming a light-absorbing film on a transparent substrate, and irradiating the light-absorbing film with light from a flash lamp at an energy density of 3 to 40 J / cm2. A photomask is prepared by forming a resist pattern on the photomask blank by photolithography, etching away those portions of the light-absorbing film which are not covered with the resist pattern, and removing the resist.
Owner:SHIN ETSU CHEM IND CO LTD

Lens cap for a transistor outline package

A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall thickness of less than 0.2 mm and a thinned area surrounding the lens so that in the thinned area the wall thickness is reduced by at least 35%.
Owner:SCHOTT AG

Thin film transistor

A thin film transistor is disclosed, comprising a substrate, a polysilicon layer overlying the substrate, a gate insulating layer overlying the polysilicon layer, a gate electrode, a dielectric interlayer overlying the gate electrode and gate insulating layer, and a source / drain electrode overlying the dielectric interlayer. Specifically, the gate electrode comprises a first electrode layer overlying the gate insulating layer and a second electrode layer essentially overlying an upper surface of the first electrode layer. The first and second electrode layers each has substantially the same profile with a taper angle of less than about 90 degrees.
Owner:AU OPTRONICS CORP

Trocar holder

A trocar holder for a manipulator of a robotic surgical system. The trocar holder comprises a base element for securing the trocar holder to the manipulator and a clamp element which is replaceably connected to the base element via a coupling mechanism. Two limbs movable relative to each other in a clamp plane are formed on the clamp element. The limbs are connected via a spine and have free tips. The trocar holder also has a clamp mechanism for opening and closing the limbs and a receiving element for a trocar.
Owner:AVATERAMEDICAL GMBH

Bipolar transistor

A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
Owner:TEXAS INSTR INC

Reduction of wafer bow during growth of epitaxial films

InactiveUS20180358221A1Reducing wafer bowRelieve in-plane stressOptical wave guidancePolycrystalline material growthWaferingWafer bow
Structures and methods for reducing wafer bow during heteroepitaxial growth are described. Micro-trenches may be formed across a surface of a substrate and filled with polycrystalline material. Stress-relieving regions of material can be grown over the polycrystalline material in a layer of semiconductor material during heteroepitaxy.
Owner:MACOM TECH SOLUTIONS HLDG INC

Semiconductor integrated circuit structure including dielectric having negative thermal expansion

A semiconductor IC structure includes a semiconductor substrate, a multi-layered dielectric structure disposed on the semiconductor substrate, a first conductive layer disposed in the multi-layered dielectric structure, and a second conductive layer disposed on the multi-layered dielectric structure. The multi-layered dielectric structure further includes a first dielectric layer disposed on the semiconductor substrate, and a second dielectric layer disposed on the first dielectric layer. A coefficient of thermal expansion (CTE) of the first dielectric layer is larger than zero, and a CTE of the second dielectric layer is smaller than zero.
Owner:UNITED MICROELECTRONICS CORP
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