36results about How to "Simplify layout and routing" patented technology

The invention relates to a method and circuit for controlling output voltage of an isolated AC-DC (Alternating Current-Direct Current) power supply. The circuit can use a two-winding transformer (T2), wherein a PWM (Pulse Width Modulation) control chip (U2) in the circuit comprises an output voltage evaluation unit, a current comparison and logic control unit and a demagnetizing time detection unit, wherein the output voltage evaluation unit and the current comparison and logic control unit are electrically connected sequentially from input to output, and the demagnetizing time detection unit is located between the output voltage evaluation unit and an output terminal of the PWM control chip (U2) and is used for detecting the conducting time t1 and demagnetizing time t2 of the transformer. The method comprises the step of enabling V0 to reach a set value by using the relationship (represented by an equation shown in a drawing) among the output voltage V0 of the transformer, VAC, t1, t2 and the turns ratio n of the transformer. The method and the circuit have the advantages that the cost of a system is reduced, and the layout and wiring of the system are simplified.

The invention discloses a focal plane assembly capable of realizing same viewing field splicing, belonging to the technical field of aerospace optical remote sensors. The focal plane assembly comprises three imaging circuit boards, three photosensitive devices, two reflecting mirrors, two bosses and a structural frame, wherein the three photosensitive devices are respectively positioned on three imaging circuit boards and are distributed on three planes; reflecting mirrors are cross to realize twice reflection and once perpendicular incidence, thereby overcoming the detect that image elements are leaked when a big-shell photosensitive device is spliced by the traditional two-surface layout; and the physical structures of the photosensitive devices or the circuit board can be prevented from mutually interfering on the splicing direction, the photosensitive surfaces of the three photosensitive devices are connected end to end, and parts of regions of the junction are overlapped so as to realize seamless splicing. According to the focal plane assembly, three (which can be expanded to multiple pieces) photosensitive devices, especially three big-shell devices, can be subjected to seamless same viewing field splicing, the size requirement on an imaging circuit is lowered, the performance is improved, the cost is lowered, and the focal plane size is enlarged so as to enlarge the ground coverage width.

The invention provides a surge protection circuit integrated in a chip. The surge protection circuit integrated in the chip comprises a main bleeder circuit and a quick detection circuit. The main bleeder circuit comprises a first diode, a second diode, a second resistor and a first MOS (metal oxide semiconductor) tube. A cathode of the first diode is connected with a power end, an anode of the first diode is grounded through the second resistor, and a node between the first diode and the second resistor is a first node. A first connection end of the first MOS tube is connected with the power end, a second connection end of the first MOS tube is grounded, and a control end is connected with the first node. The quick detection circuit comprises a capacitor, a first resistor, a third diode and a second MOS tube. The capacitor is connected between the power end and the third diode, an anode of the third diode is grounded, and a node between the third diode and the capacitor is a second node. A first connection end of the second MOS tube is connected with the power end, a second connection end of the second MOS tube is connected with the first node, and a control end is connected with the second node. Compared with the prior art, the surge protection circuit integrated in the chip has the advantage that surge protection of an internal circuit of the chip can be realized.

The invention discloses an FPGA-based method for transmitting and confirming UDP real-time data from a point to multiple points, which comprises the following steps: (1) firstly, a real-time data collecting and controlling system, which is composed of a plurality of process-quantity collecting and controlling terminals, an FPGA-based communication controlling device and one or multiple upper-layer data processing devices, is established; (2) Secondly, a universal network interface card and a real-time operating system (RTOS) are configured in an industrial personal computer system so as to constitute the upper-layer data processing devices; (3) an ACK field is added into the header of application data of a UDP datagram which is from the communication controlling device to the upper-layer data processing devices; (4) after receiving the UDP datagram of the upper-layer data processing devices, the communication controlling device transmits and arbitrates the UDP datagram; and (5) after receiving the UDP datagram, the data processing devices check the self-related values in the ACK field; if the value is 1, then the current frame is confirmed, otherwise, the current frame is retransmitted after the timer overflow is sent.

The invention discloses a decoder control circuit and a layout designing method for a Nor flash memory. The decoder control circuit is small in occupied layout area, simple in control principles and structure, uncomplicated in locating and wiring, small in the area of a peripheral drive circuit, short in reading path and fast in reading speed. In particular, the decoder control circuit of the invention has obvious area cost advantage, good reusability and easy expandability when applied to large-capacity Nor Flash memories prepared by using an advanced process.

The invention relates to a power supply system and a power supply method in SDI mode. The system includes a control module and an SDI power supply module connected to the control module. The SDI power supply module detects the voltage and current signals input by the connected video input device and transmits them to the control module, and then the control module detects the voltage and current according to the detection module. The signal controls the working mode of the SDI power supply module; the SDI power supply module includes a power supply switch, a power switch, a first power supply, a second power supply and a first resistor, and one end of the power supply switch is respectively connected to the first power supply and the second power supply through the power supply switch , the other end of the power supply switch is connected to the first resistor, and the SDI power supply module realizes detection of voltage and current signals input by the video input device through the first resistor. The invention can reduce the wiring of the video monitoring, can realize the power supply of the camera and the signal transmission of the video by using a coaxial cable, improves the reliability of the system work and simplifies the layout and wiring of the system.

A SoPC chip self-reconfiguration soft configuration method, the SoPC chip self-reconfiguration soft configuration circuit technology is studied, and a SoPC chip self-reconfiguration soft configuration method is proposed, and the method of the invention fully utilizes the characteristics of the controllability of the configuration interface , connect the GPIO interface of the processor with the configuration interface of the FPGA chip, construct the physical data path and configuration link, realize the configuration timing and configuration data by controlling the signal output and collection of the GPIO interface, and change the interface level, and complete self-reconfiguration operate. Compared with the traditional reconfiguration configuration method, the method of the present invention can realize the autonomous reconfiguration operation of the system without adding an FPGA-specific configuration chip to the SoPC chip, effectively reducing the volume of the SoPC chip, and at the same time, the interior of the SoPC chip is used for control and realization. There are fewer signals for autonomous reconfiguration operations, which reduces design complexity.

The invention discloses a device for mixing hard disk control signals via a controller. The device comprises the controller and a hard disk backboard; at least a group of connection trough positions for connecting the controller; each group of connection troughs comprises a hard disk trough position for connecting a hard disk connector and an ID identification trough position for identifying the group of connection trough positions; connection pins adapted to the connection slot trough positions on the hard disk backboard are arranged on the controller; the connection pins comprise hard disk pins adapted to the hard disk trough positions and ID identification pins adapted to the ID identification trough positions; a management chip which is connected with the connection pins is arranged inthe controller; and at least one set of indicator codes which are same as the connection trough positions in the aspect of quantity and which are used for setting a hard disk corresponding to each control signal are burnt in the management chip. The device is capable of simplifying the Layout routing, decreasing the board layers and saving the cost.

The invention discloses a lawn lamp control circuit with three ports for control. The control circuit comprises a charging circuit, a light-operated circuit, a boosted circuit and an output feedback power supply circuit. The output feedback power supply circuit is used for achieving the purpose that stable currents are supplied for elements of the control circuit through electric energy generated after solar energy or wind energy is converted all the time under any state, and other external power sources are not needed for supplying power. In addition, after the output feedback power supply circuit is used for supplying power for the control circuit, one power supply port is eliminated, and therefore locating and wiring of the control circuit are simplified, and system cost is lowered.

The present invention discloses a MIPI C-PHY signal generation method, device and system. The method includes the steps of: 1) receiving C-PHY signal start parameters and image source data, and performing data management and flow control according to the start parameters; 2) Encapsulate the code stream in the startup parameters to form an LP signal package; 3) perform one-hot encoding on the data of the LP signal package, and map the encoded LP signal to 3-wire for transmission; 4) convert the image source Encapsulate the data, distribute the packaged HS signal to each lane; 5) encode the HS signal and then output it, convert the parallel HS signal into serial output of each wire line; 6) convert the high-speed signal and The low-speed signals are mixed to form a C-PHY signal source and output to the module. The present invention supports a maximum of 6 lanes in parallel, and the data transmission speed of each lane is 17.1Gbps, which meets the throughput requirements of C-phy modules with any resolution on the market. It has strong adaptability, simple layout and wiring, and low hardware cost. It is worthy of popularization and application. .