Memory error-detecting and error-correcting coding circuit and method for reading and writing data utilizing the same

Abstract

This invention relates to an error-check and error-correction code circuit for storages and a method for reading and writing data by it taking matrix G as a logic core including: a decoding process and a coding process and a method for writing in data by this method. Apart from a decoding process and an error correction process, it also includes a coding process, and finally puts forward an error check and correction and coding circuit for realizing said two methods including a decoder, an error-correction circuit, a coding circuit, an interface circuit and related data transmission circuit so as to simplify layout of bottom circuit and speed up operation speed of circuits.

Description

technical field [0001] The present invention relates to a method for implementing ECC in a storage device, in particular to a method for reading data from a memory for error detection and correction, and a method for processing data written into memory by using the above method, and finally to realize the above-mentioned The circuit structures corresponding to the two methods. Background technique [0002] With the development of integrated circuits, memory cells will occupy most of the chip area. Storage performance has a great impact on chip performance, so it is necessary to ensure 100% accuracy of stored data. However, any memory is faced with the challenges of reliability and yield, such as the decrease of signal-to-noise ratio with the increase of integration density; soft errors caused by cosmic rays to memory cells; process deviation and material defects lead to lower memory yield, etc. Wait. Therefore, an effective method is needed to solve these problems. [00...

AI Technical Summary

Problems solved by technology

For example: environmental deterioration (voltage fluctuations, temperature rise) causes data errors; process disturbances cause parameter changes, resulting in read and write failures; other random errors, etc.

[0004] Most of the existing ECC methods do not optimize the G matrix and do not simplify the redundant data. When the process size becomes smaller and smaller, the "side effects" of the ECC circuit without upper-level preprocessing are highlighted——circuit Complex and huge, the connection area is too large; redundant bits occupy too much memory capacity, resulting in large circuit delays and affecting speed

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