Layout and wiring method, device and equipment and readable storage medium

Abstract

The invention discloses a layout and wiring method and device, equipment and a readable storage medium. According to the method and the device, for the functional module of which the data processing logic is matched with the star topology structure, the constraint modes with different constraint capabilities can be utilized to constrain each sub-module in the functional module to perform layout and wiring according to the star topology structure, so that each layout and wiring result is obtained; then, the layout wiring result meeting the preset index requirement is selected from all the layout wiring results to serve as the layout wiring scheme of the function module, layout wiring in the module can be simplified, the probability of occurrence of problems such as winding congestion, short circuit, time delay and function errors is reduced, line resources, chip power consumption and chip area are saved, and the production efficiency is improved. And a layout and wiring scheme meeting the preset index requirement can be selected, so that the performance, manufacturability and time sequence convergence effect of the chip can be improved. Correspondingly, the invention also provides a layout and wiring device, equipment and a readable storage medium, which also have the above technical effects.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a layout and wiring method, device, equipment and readable storage medium. Background technique [0002] At present, the wiring method of functional modules with complex data interaction logic usually has the following problems: the internal winding congestion of the module is serious, problems such as short circuits and time delays are prone to occur, and line resources are tight. Therefore, it is easy to cause functional errors, resulting in increased power consumption of the chip. If EDA tools are used to solve the winding problem, a certain chip area will be sacrificed. [0003] Therefore, how to simplify the layout and wiring of functional modules with complex data interaction logic is a problem to be solved by those skilled in the art. Contents of the invention [0004] In view of this, the object of the present application is to provide a layout and wiring ...

AI Technical Summary

Problems solved by technology

[0002] At present, the wiring method of functional modules with complex data interaction logic usually has the following problems: the internal winding congestion of the module is serious, problems such as short circuit and time delay are prone to occur, and line resources are tight

Therefore, it is easy to cause functional errors, resulting in increased power consumption of the chip

If EDA tools are used to solve the winding problem, a certain chip area will be sacrificed

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