Multi-concurrent RAM data transmission method and structure of X-type link structure

Abstract

The invention provides a multi-concurrent RAM data transmission method and structure of an X-type link structure. The method comprises the following steps: mapping a plurality of physically independent sub-RAMs into a shared storage RAM; obtaining an interface corresponding to each core of the on-chip multi-core processor based on shared storage; arranging a multi-stage link transmission structurebetween the interface and the sub RAM, wherein each stage of link transmission structure is provided with a plurality of X-shaped structure routers; and forming a fixed transmission path between eachinterface and each sub RAM through the X-type structure router so as to send or respond to a data stream. According to the invention, the problem of difficult layout and wiring caused by too large area of the existing multi-concurrent RAM circuit and too complex arbitration circuit is solved, routing FIFO and arbitration circuit are not needed, so that the hardware resource overhead is small, only a small number of fan-in and fan-out x-type routers are provided, the layout and wiring are simplified, and the main frequency of the circuit is effectively improved.

Description

technical field [0001] The invention relates to the technical field of data storage and transmission, in particular to a multi-concurrent RAM data transmission method and structure of an X-type link structure. Background technique [0002] Under the dual promotion of technology and application, on-chip multi-core processors (Chip Multiple Processors; CMP for short) have become the current development trend of high-performance processors, from Application Specific Integrated Circuit (ASIC) to Field Programmable Field Programmable GateArray (hereinafter referred to as: FPGA), from the cloud to the edge. The efficient data interaction between multiple cores in CMP is generally based on a parallel architecture of shared storage (multiple processors can share one memory), that is, multiple concurrent RAMs. This part has become the key to the high computing performance of CMP. [0003] Existing multi-concurrency RAMs are implemented based on fully connected networks, such as fig...

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Problems solved by technology

[0004] The present invention provides a multi-concurrent RAM data transmission method and structure of an X-type link structure, which solves the problem that the existing multi-concurrent RAM circuit area is too large and the arbitration circuit is too complicated, resulting in difficult layout and wiring. Compared with the existing technical solutions , the solution of the present invention does not need routing FIFO and arbitration circuit, so the hardware resource overhead is small, and only a small amount of fan-in and fan-out x-type routers simplify layout and wiring and effectively increase the main frequency of the circuit

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