The invention relates to a field programmable gate array (FPGA) based method for achieving synchronous detection of an oversampling Golay sequence. A hardware system established on the basis of FPGA comprises a Golay sequence detector module, a parameter read control module, a system control module, a related judgement and locking module, a time delay module and a sequence extraction module, the Golay sequence is used as a synchronous sequence, the possibility of false synchronization and false loss of synchronism can be reduced, a detecting module uses a special not exclusive or algorithm, 50% of shifting registers occupied by a slippage correlation operation can be freed, by means of the parameter read control module, multiplexing of correlation operation of the Golay sequence with various lengths and parameters is achieved, similarly, FPGA on-chip resources occupied by a synchronizing system are reduced, the sequence detection operation interval can be flexibly adjusted by the system according to different oversampling ratios, and the synchronous detection supporting 1 to 16 times oversampling is achieved.