44results about How to "Reduce connection complexity" patented technology

The multiplying adder comprises a parallel-serial multiplier and a digital serial adder. The parallel-serial multiplier includes following components: a re-coder receives the multiplier, and outputs a ordered sequence re-coded; a partial product generator generates multiple partial products based on multiplicand and the said ordered sequence re-coded; a adder adds multiple partial products in order to synthesize the product. When partial products are carried out summation, the adder outputs least significant digit in intermediate sum of partial product in digital serial format. The digital serial adder includes a carry save adder for receiving product and input of accumulator in order to generate a output. The said output is a sum of the product of input of the accumulator.

Embodiments of the present invention disclose a display panel and a display device, the display panel comprising: a display screen (1), comprising: an array substrate; an opposed substrate, cell-assembled with the array substrate to form the display screen; a circuit board (2), provided with a control circuit (5) for controlling the display screen thereon; and a wireless network adapter (3), receiving signals via a wireless network.

The invention discloses satellite task system testing equipment based on a field programmable gate array (FPGA) architecture. The testing equipment comprises a master control module, a TM and TC module, a power supply module, a direct instruction module, a temperature control monitoring module, an OC instruction monitoring module and an analog quantity module. All the hardware modules can be integrated into primary and secondary boxes, the primary box can be independently applied to a stand-alone test, and the secondary box is matched with the primary box for testing and is used for finishing the test of a satellite task subsystem; the operations of the various modules are scheduled in a unified mode by the master control module, only a computer is required during the test, and seamless connection between equipment is realized; compared with a conventional testing system, the testing equipment has the advantages that the number of the equipment is reduced, that the wiring complexity is reduced, and that the testing stability, safety and operability are improved; meanwhile, the testing equipment meets the design requirement on portability.

The invention discloses a safety controller for a welding robot and a control method thereof. The safety controller comprises a safety protection module, an upper computer, an execution module, a running information acquisition module and a field bus, wherein, the upper computer and the running information acquisition module send a parameter initialization data command and a robot running state command to the safety protection module via the field bus; the safety protection module sends alarm and error indication to the upper computer via the field bus; and the execution module receives output of the safety protection module. The safety controller and the control method thereof have the beneficial effects that connection complexity is greatly reduced by adopting a field bus technology; and a safety area protection function is realized by means of a plurality of safety protection strategies, namely, corresponding alarm or error message prompt is given out in case of abnormalities, and meanwhile corrective measures or emergency shutdown are carried out, thus ensuring safety operation of a system.

The present invention is applicable to the technical field of electronics, and provides a wireless access control management system and a wireless access control management method, the system comprises a radio frequency SIM card memory module, an iris identification module and a smart door lock, the iris identification module comprises a radio frequency SIM card read head, an iris identification device and a processor; the processor reads preset verification iris information stored in an external radio frequency SIM card in a current read head area via the radio frequency SIM card read head; the iris identification device collects current to-be-verified iris information; the preset verification iris information and the current to-be-verified iris information are compared; and if the preset verification iris information and the current to-be-verified iris information are consistent, an unlocking signal is sent to the smart door lock. The radio frequency SIM card is used for storage of user's iris information, the level of information security can be ensured, and the cost for building of data storage servers and server networks can be saved.

A non-blocking expansion system and method based on multiple disjoint unidirectional optical fiber ring networks, the system includes three stages: an input stage, an intermediate stage and an output stage, wherein both the input stage and the output stage are composed of space division switching modules; The intermediate stage is composed of multiple disjoint WDM switching modules including the unidirectional optical fiber ring network, allowing arbitrary input-to-output mapping; the connection of the intermediate stage unidirectional optical fiber ring conforms to the basic characteristics of the Clos network, and is logically consistent with the input The output stages are connected one by one through optical fiber ports; the number n of the input and output stage module ports should be consistent, and the number should not be greater than the number M of the intermediate stage switching modules. At the same time, a specific implementation method of using the system to complete non-blocking expansion is provided. The invention increases network capacity at low cost and high efficiency, flexibly and effectively utilizes all optical fiber ring link resources, improves the utilization rate of wavelength resources in the network, eliminates network blocking rate, and is beneficial to the realization of future high-performance optical networks.

The invention belongs to the technical field of wireless digital communication and broadcasting, and particularly provides a high-performance and low-complexity LDPC decoder based on randomized computation. The decoder supports an IEEE802.16 (WiMAX) standard and structurally comprises a look up table (LUT) array of NDS coefficients suitable for a (576 and 480) check matrix in the IEEE802.16 (WiMAX) standard, a VN array with the EM initialization function and a saturating counter with computation posteriori information and SM. An information spreading decoding algorithm based on randomized computation is adopted in the decoder, and the wiring complexity of the decoder can be effectively lowered and the area utilization rate of a chip can be increased while the requirement for a current communication standard throughput rate is met; meanwhile, the decoder selects proper NDS parameters and improves a randomized computation hardware structure according to the specific check matrix, initialization time is shortened, the convergence speed is increased, the decoding performance of randomized computation of the decoder is improved, decoding time is shortened, and the throughput rate is increased.

The present application relates to a power line signal transmission method, device and transmission electrical equipment. The method includes: receiving a communication signal and a power supply voltage; coupling the power supply voltage and the communication signal to obtain a carrier signal; and transmitting the carrier signal to the controlled side through a power line. By coupling the power supply voltage on the control side with the communication signal, the carrier signal is obtained, and then the carrier signal is transmitted to the controlled side through the power line carrier to realize the power line carrier transmission. The communication line and the power line can be integrated, thereby reducing The number of connection lines between the control side and the controlled side reduces the connection complexity and improves the connection convenience between the control side and the controlled side.

The invention discloses a decoder control circuit and a layout designing method for a Nor flash memory. The decoder control circuit is small in occupied layout area, simple in control principles and structure, uncomplicated in locating and wiring, small in the area of a peripheral drive circuit, short in reading path and fast in reading speed. In particular, the decoder control circuit of the invention has obvious area cost advantage, good reusability and easy expandability when applied to large-capacity Nor Flash memories prepared by using an advanced process.