74 results about "Carry-save adder" patented technology

A floating point unit 10 provides a multiply-accumulate operation to determine a result B+(A*C). The multiplier 20 takes several processing cycles to determine the product (A*C). Whilst the multiplier 20 and its subsequent carry-save-adder 26 operate, an aligned value B' of the addend B is generated by an alignment-shifter 34. The aligned-addend B' may only partially overlap with the product (A*C) to which it is to be added using an adder 44. Any high-order-portion HOP of the aligned-addend B' that does not overlap with the product (A*C) must be subsequently concatenated with the output of the adder 44 that sums the product (A*C) with the overlapping portion of the aligned-addend B'. If the sum performed by the adder 44 generates a carry then it is an incremented version IHOP of the high-order-portion that should be concatenated with the output of the adder 44. This incremented-high-order-portion is generated by the adder 44 during otherwise idle processing cycles present due to the multiplier 20 operating over multiple cycles.

The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to N+1 bits. A circuit for determining the output carry value associated with the result is also provided.

A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication.

Montgomery multiplication can be computed quickly by using carry save adders and parallel multipliers. We present an enhanced technique for very fast Montgomery multiplication that can be used for RSA calculations. This invention utilizes a scalable bit word implementation, suitable for very large bit encryptions. Such designs can be deployed on mid-level FPGAs that have dedicated multiplier logic, on ASICs, or on custom circuits. To our knowledge, our technique yields some of the fastest RSA encryption times to be reported, having area requirements similar to related work. Such circuits can be ideal for increased security in sensitive communication fields.

The invention discloses a base-16 fixed point divider based on a carry-save adder and belongs to the technical field of computer digital. The base-16 fixed point divider based on the carry-save adder comprises a detecting-relocating module, a quotient loop generating module, a quotient conversion module, a quotient / remainder adjusting module and an execution control module. According to the base-16 fixed point divider based on the carry-save adder, data is received and regularized through the detecting-relocating module and shifts leftwards. The received regularized data is used for loop operation, and loop iteration generates redundant data. The redundant form quotient value generated by the quotient loop generating module is received. Standard binary complementary form is converted by adoption of the carry-save form. Symbol same sign adjustment is conducted on the quotient result and the remainder result according to the RNS algorithm, and the quotient is adjusted. Finally, corresponding figure is shift rightward after the operation is realized, the result is input in a counter, and the loop execution times are calculated. The path delay of the one-bit generated by the base-16 fixed point divider based on the carry-save adder can be greatly shortened, one time of loop operation can generate four-bit quotient value due to the simple configuration of the divider, and the operating efficiency is improved.

A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.