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A multiplier, 2n-1 technology, applied in the direction of calculation using non-contact manufacturing equipment, calculation using number system representation, etc., can solve the problems of low speed and resource consumption, so as to improve the calculation speed and reduce resource consumption Effect
Inactive Publication Date: 2011-11-23
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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[0006] The purpose of the invention is in order to solve the existing mold-oriented (2 n -3)
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[0019] The present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.
[0020] The mold of the present invention (2 n -3) The multiplier structure is shown in Figure 1, wherein, 1 is an n-bit binary multiplier, 2 is an n-bit CSA (Carry Save Adder) compressor array, 3 is an n-bit binary adder with carry input, and 4 is a 2-bit adder, 5 is the first n-bit binary adder, 6 is the second n-bit binary adder, A [n-1:0] and B [n-1:0] For an input of 1, P [2n-1:0] output of 1; P [n-1:0] ,P [2n-1:n] and P [2n-2:n#2n-1] For 2 inputs, L [n-1:0] and H [n-2:0#n-1] is the output of 2; L [n-1:0] 、H [n-2:0#n-1] and H [n-1] For 3 inputs, R [n:0] is the output of 3; P [2n-1] #H [n-1] and R [n] #R [n] For an input of 4, G [2:0] is the output of 4; R [n-1:0] and G [2:0] For 5 inputs, T [n:0] is the output of 5; T [n-1:0] and T [n] #T [n] For 6 inputs, Y [n-1:0] for the output of 6.
[0021] For the specific con...
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Abstract
The invention belongs to the field of computers and integrated circuits and discloses a modular (2<n>-3) multiplier, which specifically comprises an n-bit binary multiplier (1), an n-bit carry save adder (CSA) compressor array (2), an n-bit binary adder (3) with carry input, a two-bit adder (4), a first n-bit binary adder (5) and a second n-bit binary adder (6). The modular (2<n>-3) multiplier reprocesses by using a result of binary multiplication as an operation number P, so multi-time modification of the conventional modular (2<n>-3) multiplier is changed into one-time modification, consumed resources of the modular (2<n>-3) multiplier are greatly reduced, and the operation speed of the modular (2<n>-3) multiplier is improved.
Description
technical field [0001] The invention belongs to the field of computers and integrated circuits, and in particular relates to the design of a high-speed multiplier. Background technique [0002] Before introducing the multiplier, first explain the Residue Number Systems (RNS, Residue Number Systems). The remainder system RNS is a numerical representation system that describes numbers through the remainder of a set of pairwise coprime remainder bases. by {m 1 , m 2 ,...,m L} composed of L remainder bases, integer X, 0≤X<M, where M=m 1 × m 2 ×…×m L , there is a unique expression in the RNS system as X={x 1 , x 2 ,...,x L}, in Denotes X for modulo m i remainder of . To operate on two operands in the remainder system, the operator is Θ, which can be defined as: [0003] {z 1 ,z 2 ,…,z L}={x 1 , x 2 ,...,x L}Θ{y 1 ,y 2 ,...,y L},in Here Θ can be modular addition, modular subtraction or modular multiplication. In a remainder system these arithmetic op...
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