106results about How to "Minimize the effect of parasitic capacitance" patented technology

Provided are a Micro Electro-Mechanical System (MEMS) package and a method of packaging the MEMS package. The MEMS package includes: a MEMS device including MEMS structures formed on a substrate, first pad electrodes driving the MEMS structures, first sealing parts formed at an edge of the substrate, and connectors formed on the first pad electrodes and the first sealing parts; and a MEMS driving electronic device including second pad electrodes and second sealing parts respectively corresponding to the first pad electrodes and the first sealing parts to be sealed with and bonded to the MEMS device through the connectors to form an air gap having a predetermined width.

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a semiconductor layer located on the substrate, a source and a drain located on the semiconductor layer, a gate located between the source and the drain, a source field plate located on the semiconductor layer and connected with the source, wherein the source field plate passes across the gate, the gate/source region and part of the gate/drain region, and air isolation is carried out; one end of the source field plate is connected with the source; two or more than two metal field plates are connected in parallel to form connection between the source field plate and the source; and the other end of the source field plate is located on the semiconductor layer, close to the gate, between the gate and the drain. A role of electric field modulation of the source field plate can be fully played, parasitic gate/source capacitance and parasitic conduction resistance can be fully reduced, and reliability of the device is improved.

The embodiment of the invention discloses a calibrating circuit. The calibrating circuit comprises a reference voltage generation circuit, a capacitor charging and discharging circuit, a voltage comparer and a digital control circuit, wherein the capacitor charging and discharging circuit and the voltage comparer are connected with the reference voltage generation circuit; the capacitor charging and discharging circuit is connected with the voltage comparer; the digital control circuit is connected with the voltage comparer; the digital control circuit is connected with the capacitor chargingand discharging circuit; the reference voltage generation circuit is used for generating a first reference voltage, a second reference voltage and a third reference voltage, and buffering the first reference voltage to obtain a first voltage; the capacitor charging and discharging circuit is used for generating a second voltage according to the first voltage, the second reference voltage and a received first clock signal; the voltage comparer is used for comparing the second voltage with the third reference voltage to obtain a voltage comparison output signal; and the digital control circuit is used for generating a first digital control signal, a second digital control signal and a third digital control signal according to the voltage comparison output signal. The embodiment of the invention further discloses a calibrating method.

The invention discloses an ultra high speed laser driver circuit with bandwidth compensation and a diver chip; the feedback circuit composed of two cross coupling capacitors and the capacitor and the resistor connected in a parallel mode is used for executing the laser driver bandwidth compensation. For two cross coupling capacitors, the stray capacitance between the base and the collector can be eliminated; for the feedback mode of one capacitor and one resistor, one zero point is generated for compensating the pole for realizing the bandwidth compensation; and the modulating current directly flows to the laser diode through the load resistor, so that the laser diode can obtain larger modulating current. The laser driver circuit and the driver chip having pre-emphasis function are simple in structure, high in bandwidth, large in modulating current and low in power consumption; the chip adopts the resistor and capacitor for expanding the bandwidth, the occupied area is small and the chip cost is reduced; the work speed is 40Gb/s through the 0.13 mum BiCMOS process certification and the output modulating current is greater than 10 mA.

A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.

In a capacitor and a capacitor array configured for reducing an effect of parasitic capacitance, the capacitor array can have a matrix configuration that includes a plurality of unit capacitors. The unit capacitors include a lower electrode and an upper electrode that constitute a plate capacitor, as well as shielding structures which enclose the capacitor. The unit capacitors are connected by an upper electrode connecting line with a first direction to constitute a plurality of capacitor columns, wherein the unit capacitors are also arranged in rows, in a second direction perpendicular to the first direction, and wherein lower electrode lead lines are disposed between the capacitor columns, the lower electrode lead lines being connected to the respective lower electrodes of each of the unit capacitors.

A signal transmission structure suitable for a multi-layer circuit substrate comprising a core layer and at least a dielectric layer is provided. The signal transmission structure according to the present invention comprises a first via landing pad and a reference plane. The first via landing pad is disposed on a first surface of the core layer, and covering one end of the through hole of the core layer. The dielectric layer covers the first via landing pad and the first surface of the core layer. And the first reference plane is disposed above the dielectric layer, having a first opening disposed above one end of the through hole. Wherein, the area where the first reference plane is projected on the first surface of the core layer does not overlap with the area where the first via landing pad is projected on the first surface of the core layer.

A semiconductor substrate and a semiconductor device are disclosed. The semiconductor substrate includes a base layer, a buffer layer disposed on the base layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a buried field plate region embedded in the channel layer. In an embodiment, the channel layer includes a two-dimensional electron gas (2DEG), and the buried field plate region is located below the two-dimensional electron gas.

A high resistance re-grown layer is disposed around an optical device having a mesa structure. Thus, a mesa portion having a plane direction that appears in etching of a circular main structure is coated with the re-grown layer. Because of this coating, it is possible to reduce the capacitance in this portion as well as to avoid the risk of disconnection with respect to all the wiring directions. The thickness of the re-grown layer can be set to be equal to the thickness of the main structural part. Particularly, when a conductive substrate is used, a substantial reduction effect of parasitic capacitance can be expected from a combination with plural dielectric films.