An
integrated circuit package includes an
inductance loop formed from a connection of lead wires and one or more input / output (I / O)
package pins. In one embodiment, the
inductance loop is formed from first and second wires which connect a first bonding pad on the
integrated circuit chip to a first I / O pin of the
package and a third and fourth wires which connect a second bonding pad on the
chip to a second I / O pin of the package. To complete the
inductor loop, the first and second I / O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I / O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I / O pins based, for example, on loop-length requirements, space considerations, and / or other design or functional factors. In another embodiment, connection between the first and second I / O pins is established by making the I / O pins have a unitary construction. In another embodiment, connection between the first and second I / O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the
inductor loop within the limits of the
integrated circuit package, a substantial reduction in
space requirements is realized, which, in turn, promotes
miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the
inductor loop of the package.