108results about How to "Increase readout speed" patented technology

Imaging sensors having dual-port for digital readout to pipeline readout processes of two different groups of pixels.

An image sensor includes a plurality of operation circuits. The operation circuit operates pixel signals read out from a group of pixels included in a readout area to generate a pixel signal in the thinning readout mode. A plurality of column selecting switches are arranged between the output terminals of the plurality of operation circuits and a plurality of output channels. A control circuit controls the plurality of column selecting switches such that pixel signals the number of which is equal to the number of the plurality of output channels are output to the plurality of output channels in parallel in the thinning readout mode. The circuit arrangements, each included in the corresponding one of the plurality of operation circuits and each viewed from the corresponding one of the column selecting switches used in the thinning readout mode, are equivalent to each other.

An image sensor has a plurality of pixels arrayed to form a plurality of columns. The sensor includes a plurality of readout circuits which generate pixel signals based on signals supplied from the pixels of respective columns, a plurality of output channels, a plurality of column selecting switches, and a control circuit which controls the plurality of column selecting switches. The control circuit controls the plurality of column selecting switches so as to output the pixel signals of target readout pixels to output channels selected based on a selection rule in the spatial order of the pixels in the full pixel readout mode. The control circuit controls the plurality of column selecting switches so as to output the thinned-out pixel signals of target readout areas to output channels selected based on the same rule as the selection rule in the spatial order of the areas in the thinning readout mode.

The present invention provides a secured document including a composition capable of anti-Stokes fluorescence containing an ion capable of absorption of electromagnetic radiation, an ion capable of emitting electromagnetic radiation, and a matrix composition comprising gadolinium, yttrium, lanthanum, and lutetium, wherein the wavelength of the emitted electromagnetic radiation is shorter than the wavelength of the absorbed electromagnetic radiation, and wherein the concentrations of the absorbing and emitting ions are adjusted to achieve concentration quenching of anti-Stokes luminescence.

A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells / bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

The present invention provides a secured document including a composition capable of anti-Stokes fluorescence containing an ion capable of absorption of electromagnetic radiation, an ion capable of emitting electromagnetic radiation, and a matrix composition comprising gadolinium, yttrium, lanthanum, and lutetium, wherein the wavelength of the emitted electromagnetic radiation is shorter than the wavelength of the absorbed electromagnetic radiation, and wherein the concentrations of the absorbing and emitting ions are adjusted to achieve concentration quenching of anti-Stokes luminescence.

An image sensor includes a plurality of operation circuits. The operation circuit operates pixel signals read out from a group of pixels included in a readout area to generate a pixel signal in the thinning readout mode. A plurality of column selecting switches are arranged between the output terminals of the plurality of operation circuits and a plurality of output channels. A control circuit controls the plurality of column selecting switches such that pixel signals the number of which is equal to the number of the plurality of output channels are output to the plurality of output channels in parallel in the thinning readout mode. The circuit arrangements, each included in the corresponding one of the plurality of operation circuits and each viewed from the corresponding one of the column selecting switches used in the thinning readout mode, are equivalent to each other.

When write data D is high rewritten data, a PC 10 controls a DRAM 24 to store the write data D (steps S100 and S110). When the write data D is not the high rewritten data, the PC 10 outputs an RRAM write request signal and the write data D to an SSD (step S100 and S120). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.

When write data D is high rewritten data, a PC 10 controls a DRAM 24 to store the write data D (steps S100 and S110). When the write data D is not the high rewritten data, the PC 10 outputs an RRAM write request signal and the write data D to an SSD (step S100 and S120). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.

An image sensor includes a plurality of operation circuits. The operation circuit operates pixel signals read out from a group of pixels included in a readout area to generate a pixel signal in the thinning readout mode. A plurality of column selecting switches are arranged between the output terminals of the plurality of operation circuits and a plurality of output channels. A control circuit controls the plurality of column selecting switches such that pixel signals the number of which is equal to the number of the plurality of output channels are output to the plurality of output channels in parallel in the thinning readout mode. The circuit arrangements, each included in the corresponding one of the plurality of operation circuits and each viewed from the corresponding one of the column selecting switches used in the thinning readout mode, are equivalent to each other.

The respective sources of drive transistors included in memory cells that are located in each of multiple columns and connected to a corresponding one of bit line pairs are connected commonly to a low voltage power supply VSS via an assertion transistor. When data is written, the assertion transistor for the memory cells connected to a selected one of the bit line pairs and located in the identical column is negated, so that the sources of the drive transistors in the memory cells in that column are allowed to float. Consequently, even with a low power supply voltage, it is possible to write the data into a single selected memory cell, while data in the unselected memory cells can be retained favorably.

The invention discloses a sensitivity amplifier for EEPROM. It includes charge control circuit and detecting output circuit. The charge control circuit includes PMOS tube P1 and NMOS tubes N1, N2. Detecting output circuit includes PMOS tubes P2, P3 and NMOS tubes N3, N4, N5. The invention uses the bidirectional ducting ability of MOS tube to take charge to drain electrode. The source electrodes of floating grid tube are connected to each other to decrease charging circuit quantity. By modifying the reverse threshold value of the inverter, the charging voltage would be decreased, and read speed would be improved. The invention is especially suitable for embedded EEPROM.

A scheme is provided that enhances the dynamic range performance of images via multiple readouts during one exposure. The readout process circuit structure includes at least an analog-to-digital converter (ADC). The analog-to-digital converter converts analog data generated from an image sensor into digital data, allowing sub-frame readouts for improving a dynamic range of the image sensor. Additionally, methods of partial digitization (not a full number of bits) and image array are provided.

An image sensing device comprises a pixel array, and a peripheral circuit, a column selecting circuit, and a readout, wherein each pixel includes a photodiode, a floating diffusion, a transfer PMOS transistor to the floating diffusion, an amplifier PMOS transistor, and a reset PMOS transistor, the amplifier PMOS transistor has a gate which is formed by an n-type conductive pattern, and is isolated by a first element isolation region and an n-type impurity region which covers at least a lower portion of the first element isolation region, and each PMOS transistor included in the column selecting circuit has a gate which is formed by a p-type conductive pattern and is isolated by a second element isolation region, and an n-type impurity concentration in a region adjacent to a lower portion of the second element isolation region is lower than that in the n-type impurity region.

An integrated optical sensor for, for example, a (bio)chemical sensor has an optical waveguide (2) having at least two coupling regions (3, 5), which are separated by at least one measurement region (4). A first wave is excited in the waveguide (2) by the first coupling region (3) and passes through the measurement region (4) and the second coupling region (5). A second wave is excited in the second coupling region (5) and subsequently interferes with the first wave. Here, the reduction in amplitude of the first wave by the second coupling region (5) is less than 95%.

The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signal and the latch output signal, in which the pull-up circuit increases an output voltage of the output driver circuit from a ground level to a first level when the preset enable signal is at a low level and the latch output signal is at the high level.

The invention relates to a read amplification circuit for a nonvolatile memory and a memory. The read circuit comprises a basic physical unit composed of a plurality of storage units, a reference unit set and a read amplifier, wherein the storage units are correspondingly connected to respective read bit lines; the basic physical unit is gated via a first gate tube; the reference unit set has the same configuration as the basic physical unit and is composed of a plurality of reference units; the reference units and the storage units are one-to-one correspondence; the reference units are correspondingly connected with respective reference voltage lines, and respectively have the same structure as the corresponding storage units; the reference unit set is gated via a second gate tube; the second gate tube has the same structure as the first gate tube; the read amplifier is connected with the read bit lines and the reference voltage lines, and outputs corresponding read data according to the comparative result between the read bit lines and the voltages on the corresponding reference voltage lines. The read amplification circuit can enhance the data read speed when reading the memory, and prolong the service life of the memory.