45results about How to "Improve planarization" patented technology

The invention discloses a method for smoothening the surface of a wafer, including the following steps: providing a wafer which is provided with a medium layer on the surface and is composed of a central area and a marginal area surrounding the central area; removing the medium layer at the marginal area; and chemically and mechanically rubbing the whole medium layer on the surface of the wafer; wherein the thickness of the medium layer at the marginal area after being rubbed by a test piece is bigger than the depth of the etched through hole; and the removed thickness of the medium layer at the marginal area is larger than or equal to the average thickness difference tested by a test piece between the medium layer at the central area and the marginal area of the chemically and mechanically rubbed wafer. The method for smoothening the surface of the wafer reduces thickness difference between the medium layer at the central area and the marginal area of the wafer after chemically and mechanically rubbing the surface of the medium layer on the surface of the wafer, thus improving the smoothness of the surface of the wafer.

A touch sensitive device is provided. The device includes a substrate; a plurality of first electrodes formed on the substrate and arranged along a first direction without overlapping one another; a first insulating layer formed on the substrate and covering the plurality of first electrodes; and a plurality of second electrodes formed on the first insulating layer and arranged along a second direction without overlapping one another, wherein the first direction is vertical to the second direction.

The embodiment of the invention provides a liquid crystal display substrate and relates to the technical field of the liquid crystal display. According to the invention, the surface of the liquid crystal display substrate can achieve higher flat degree. The liquid crystal display substrate comprises a substrate and display parts, wherein a groove is arranged on the substrate; the display parts are formed in the groove; upper surfaces of the display parts formed at the top end in the groove are horizontal or in the same horizontal plane; when a single display part is formed at the top end in the groove, the upper surface of the single display part is horizontal; and when a plurality of display parts are formed at the top end in the groove, the upper surfaces of the display parts are in the same horizontal plane. The embodiment of the invention also provides a manufacturing method of the liquid crystal display substrate, a corresponding liquid crystal panel and a display device.

Enhanced microfabricated spring contact structures and associated methods, e.g. such as for electrical contactors and interposers, comprise improvements to spring structures that extend from the substrate surface, and / or improvements to structures on or within the support substrate. Improved spring structures and processes comprise embodiments having selectively formed and etched, coated and / or plated regions, which are optionally further processed through planarization and / or annealment. Enhanced solder connections and associated processes provide a gap between substrates for componentry, and or improved manufacturing techniques using distributed spacers. Enhanced probe card assembly structures and processes provide improved planarization adjustment and thermal stability.

A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer.

The invention relates to a forming method of a dual-damascene structure, comprising the following steps of: providing a substrate, wherein the surface of the substrate is provided with conductive areas, an inter-layer dielectric layer is formed on the substrate, through holes are formed in the inter-layer dielectric layer, and the positions of the through holes correspond to the positions of the conductive areas; forming a first anti-reflection layer on the inter-layer dielectric layer and in the through holes, and filling the contact through holes; forming a second anti-reflection layer on the first anti-reflection layer, wherein the viscosity of the second anti-reflection layer is larger than that of the first anti-reflection layer; carrying out groove imaging on the second anti-reflection layer, the first anti-reflection layer and the inter-layer dielectric layer, etching the second anti-reflection layer, the first anti-reflection and partial inter-layer dielectric layer to form a groove, wherein the bottom of the groove is communicated with at least one through hole; filling a conducting material in the groove and the through holes; and flattening the conducting material to form the dual-damascene structure.

A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed.

In a layout design method for a semiconductor integrated circuit, a cell layout library is provided which stores structure information of functional cells and a plurality of groups of filler cells, each filler cell acting to fill space between the functional cells. The functional cells are arranged on a layout based on the structural information from the layout library. The filler cells of any of the plurality of groups are arranged selectively based on the structural information from the layout library so that the filler cells are arranged in channel regions where the functional cells are not located on the layout, each channel region being located at a predetermined distance from signal lines on the layout.

The invention discloses a method for flattening the surface of a wafer, comprising: providing a wafer with a dielectric layer on the surface, including a central region and an edge region surrounding the central region; removing a partial thickness of the dielectric layer in the edge region; for the entire wafer surface The medium layer is chemically mechanically polished, wherein the edge area is the area of ​​the medium layer where the thickness of the medium layer is greater than the depth of the etched through hole after the test piece is ground, and the thickness of the medium layer in the edge area is greater than or equal to that measured by the test piece after chemical mechanical grinding. The average thickness difference between the dielectric layer in the center area of ​​the wafer and the dielectric layer in the edge area of ​​the wafer. The method for flattening the wafer surface of the present invention makes the dielectric layer on the wafer surface undergo chemical mechanical grinding, and the gap between the thickness of the dielectric layer in the edge region of the wafer and the thickness of the dielectric layer in the central region of the wafer is reduced, thereby improving the flatness of the wafer surface. degree of transformation.

Provided is a polishing liquid comprising a liquid vehicle, abrasive grains, and a polymer. The polymer has a first molecular chain where functional groups are directly bonded and a second molecular chain branched from the first molecular chain. The functional groups are at least one selected from the group consisting of carboxyl, carboxylate, hydroxyl, sulfo, and sulfonate groups.

The present invention provides: a multilayer substrate in which a spacer is selectively disposed in a non-display region without reduction in display quality or productivity of a liquid crystal display device; a production method thereof; and a liquid crystal display panel and a liquid crystal display device each using the multilayer substrate or the production method thereof. The multilayer substrate of the present invention is a multilayer substrate comprising a resin interlayer film and an electrode on a substrate in this order, wherein the multilayer substrate has a depression structure including the resin interlayer film in a surface layer, or a depression structure having a rough bottom surface on the resin interlayer film.

The invention discloses a polishing pad for solving the problems of nonuniform distribution of polishing liquid and need of further improvement of the polishing speed and the leveling degree in a traditional polishing pad. The polishing pad at least comprises a circular polishing layer; a groove for flowing the polishing liquid is formed in the upper surface of the polishing layer; the groove consists of a peripheral groove and a radial groove; the peripheral groove is a peripheral geometric center symmetry pattern with the circle center of the polishing layer as center; the edges m of the pattern are not fewer than 3; and the radial groove is a straight line or / and a curve scattered from the peripheral direction along the circle center, and has an intersecting point with the peripheral groove. The polishing pad is simple in structure, can enable the polishing liquid to uniformly distribute and flow in a polishing area, keeps uniform concentration of reactants and products in the polishing liquid in the polishing area to the greatest extent, accelerates the polishing speed, and improves the wafer planar degree.

A polishing composition that is for use in CMP polishing and that makes it possible to minimize the occurrence of defects. A polishing composition comprising silica particles, a basic nitrogen-containing organic compound, and water serving as a solvent, wherein the composition exhibits an Rsp value of the following Formula (1) of more than 0.7 and 6 or less as calculated from values measured by pulse NMR: Rsp=(Rav−Rb) / (Rb) . . . (1) (wherein Rsp is an index of water affinity; Rav is the reciprocal of the relaxation time of the polishing composition; and Rb is the reciprocal of the relaxation time of the water serving as a solvent of the polishing composition).

The invention provides a method for adding redundant graphics. The method comprises the following steps: dividing a domain into a plurality of subdomains in the same size and calculating an original density value of each subdomain; dividing the subdomains into a plurality of groups and taking the subdomains with the same or similar original density values as one group; selecting the groups in which the redundant graphics need to be added; calculating the sizes of the redundant graphics needing to be added in the subdomains of each group according to the density values; setting a scaling value and scaling each of the redundant graphics in the subdomains of the same group according to the scaling value; calculating the scaled density values of the subdomains; calculating a density difference of the original density values and the scaled density values of the subdomains; and adjusting the sizes of the redundant graphics according to an absolute value of the density difference, wherein the sizes of the redundant graphics are decreased along with the increasing of the absolute value of the density difference. According to the method, the homogeneous density distribution of wafers is ensured; the density distribution difference of the domain and the wafers is reduced, so that the flatness degree is improved.

The invention provides a method for manufacturing a flexible AMOLED display. Before making a flexible substrate on a rigid substrate, firstly, an inorganic film layer with a flat surface is formed on the rigid substrate, and then a polymeric film is coated on the inorganic film layer. material to form a flexible substrate, which can not only avoid the problem of sag and protrusion of the flexible substrate caused by impurity particles remaining on the surface of the rigid substrate due to poor cleaning, but also make the flexible substrate and the rigid substrate peel off. The substrate is easily separated from the rigid substrate to protect the flexible substrate from damage, so that the flexible substrate of the flexible AMOLED display has a higher degree of planarization, improves the water and oxygen barrier performance of the flexible substrate, and ensures flexibility. Optical properties of AMOLED displays.

The invention provides a polishing layer, a polishing pad with the polishing layer and a preparation method of the polishing layer, and relates to the technical field of polishing of chemical mechanical planarization treatment. The preparation method comprises the following steps that prepolymer of bifunctional or polyfunctional isocyanate in component A and a multi-component mixture of a hollow microsphere in component B and a curing agent in component C are prepared; forming by pouring is carried out, specifically, the multi-component mixture is poured into a mould cavity and subjected to leveling gelation; heating and solidifying are carried out, specifically, a mould loading a gelatinous ternary mixture is heated and solidified, to obtain a pouring body; and when the temperature is lowered to a predetermined temperature T, the heat preservation and slice cutting are performed, and the horizontal cutting rate V of a cutter relative to the pouring body during slice cutting meets: 8cm / s <= V<= 20 cm / s.