36results about How to "Improve jitter characteristics" patented technology

A gateway module for connection of at least two sub-networks is described. A first sub-network of the at least two sub-networks supports a data transmission in accordance with a first communications protocol, especially CAN, FlexRay, LIN, MOST or Ethernet, and a second sub-network of the at least two sub-networks supports a data transmission in accordance with a second communications protocol, especially CAN, FlexRay, LIN, MOST or Ethernet. The gateway module has a configurable hardware circuit which is adapted to manipulate and forward data from the first sub-network and to the second sub-network taking into consideration the first communications protocol and the second communications protocol.

At a first step, in a synchronous clock generation circuit, the number of delay stages serving as a digital PLL circuit is increased/decreased, and an oscillation circuit performs an oscillation operation when an optimal number of delay stages is set. Thereafter, in an operation at a second step, a control voltage is controlled with the optimal number of delay stages being set for serving as an analog PLL circuit, thereby attaining a lock-in state. As the lock-in state is finally maintained under analog control, an excellent jitter characteristic can be obtained. Thus, ensuring a lock-in range that has been a problem in the analog PLL circuit is solved by varying the number of delay stages in the operation at the first step, and a high jitter characteristic that has been a problem in a digital PLL circuit can be solved by analog control in the operation at the second step.

The object of the present invention is to provide an optical recording medium which comprises a substrate, and a first information layer and a second information layer disposed on the substrate, and an intermediate layer disposed between the first information layer and the second information layer, wherein any one of recording and reproducing is performed in the first information layer and the second information layer by irradiating a laser beam from the first information layer side, the second information layer comprises a protective layer, a second dye layer which comprises an organic dye, an oxidized layer, and a reflective layer in this order from the laser beam irradiation side, and the oxidized layer comprises an oxide which is a material constituting the reflective layer.

A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock.

A structure is provided for significantly reducing the current excessively consumed for generating a high-speed clock signal necessary for signal processing, and significantly improve the jitter characteristics of the high-speed clock signal. The structure includes a reference-clock signal generation circuit, a time-base processing circuit, a PLL circuit, and a high-speed signal processing circuit. A low-speed reference-clock signal generated by the reference-clock signal generation circuit is provided to the PLL circuit. The PLL circuit generates a high-speed clock signal by multiplying the reference-clock signal by a factor of N. The factor N is at least 100. To reduce a jitter of the high-speed clock signal generated by the PLL circuit, a natural angular frequency ωn and a damping factor ζ that relate to the response characteristics of the system of the PLL circuit are set to range from 3 kHz to 10 kHz, and 0.01 or less, respectively.

Disclosed herein is an interface receiver including: an input terminal receiving first and second data signals; a negative feedback unit negatively feeding back the first and second data signals input to the input terminal to generate first and second feedback signals; and an output terminal outputting logic level signals by using the first and second feedback signals generated by the negative feedback unit, whereby a timing margin can be secured.

The invention discloses a differential clock tree circuit for a high-speed multi-channel interface bus. The differential clock tree circuit for the high-speed multi-channel interface bus has the characteristics of being low in jitter, simple in structure, capable of being cascaded and high in anti-noise capability, and long-distance transmission of a high-speed clock can be achieved. The highly symmetric full analog differential clock tree circuit of the invention has the characteristics of being low in jitter, simple in structure, capable of being cascaded and high in anti-noise capability, and long-distance transmission of the high-speed clock can be achieved. A cascade circuit formed on the basis of the differential clock tree circuit is of a full differential structure, the differential structure appears in pairs and has strong ability to suppress noises; secondly, the structure adopted by the differential clock tree circuit is a differential input/output structure form, which canrealize cascading; thirdly, a field-effect transistor is used for bias power supply, thus noises on the power supply and ground can be shielded, and the low-jitter characteristics can be realized; andfinally, a collector series resistor of a transistor is adopted to reduce the swing amplitude of a differential signal, the driving capability is high, and long-distance transmission can be realized.

The invention relates to a PDP (plasma display panel), especially a PDP able to raise discharging efficiency and improve dither characteristic as discharging by forming addressing electrodes matching with transparent electrode structure. And the PDP comprises: a front substrate equipped with scan electrodes and sustain electrodes; a rear substrate equipped with addressing electrodes staggered with the scan electrodes and the sustain electrodes; barriers for partitioning discharging cell regions on the rear substrate, where the scan electrodes and the sustain electrodes are respectively composed of transparent electrodes and bus electrodes, and in a discharging cell, the area of the addressing electrode is more than the maximum area of the transparent electrode.