40results about How to "Improve debuggability" patented technology

The invention relates to an embedded system for real-time detecting memory, and relative method for real-time detecting memory and picking up the memory cross mistake, wherein said method comprises: starting one real-tie memory detecting proxy mission module, and initializing the memory detection; receiving background user instruction, and setting memory detecting point; then transmitting said user instructions to the real-time memory detecting proxy mission module; and when the trigger conditions are met, adjusting abnormal interruption.

A dynamic internal memory features in the fixed size internal memory page, whose size and quantity can be designated by application within system allowable scope, and the page quantity can be dynamically expanded or retracted, with application transparency. It can also support inspecting internal memory out of range and leakage of the allocation. It applies to ordinary timely system development with flexibility, highly efficient internal memory management, improving system running efficiency and robustness.

The present invention provides an on-chip debug and diagnostic method, a device and a chip. The method comprises the steps of monitoring the interrupt trigger information; generating a stop clock signal, a freeze signal and an interrupt trigger flag based on the interrupt trigger information; according to the stop clock signal, closing a functional clock; according to the freeze signal, freezing the state of a non-debug module port; upon monitoring the interrupt trigger flag, recording the state of an internal trigger and the internal state of a memory; after the recording is completed, recovering the function of the clock. Based on the on-chip debug and diagnostic method, the device and the chip, the functional clock can be automatically closed when the chip goes wrong, and the operation of a processor is paused. Meanwhile, the debug and diagnostic function is triggered automatically, so that the internal state of the chip can be quickly and accurately acquired. The debugging capability of the chip is effectively improved. therefore, the fault diagnosis is more rapid and the fault location is more accurate.

The present invention provides a temperature compensation equalization circuit of a TR assembly. The temperature compensation equalization circuit comprises a temperature compensation circuit and an equalization circuit, and the temperature compensation circuit adopts a PIN diode core and a DC bias circuit to realize a temperature compensation function. The DC bias circuit is formed by connecting a fixed resistor and a thermistor in series, the equalization circuit comprises the equalization resistors realized by a micro-strip open circuit stud and a lumped resistor on an open circuit transmission line, the equalization resistors are realized by the gold plated alumina ceramic substrates and the TaN resistive films, and the short circuit state of the two equalization resistors is realized by a gold wire welding technology. The temperature compensation equalization circuit can be applied to the ultra wide band TR assembly better, solves the problem that the ultra wide band TR assembly is large in gain fluctuation within the frequency bands and large in high-low temperature gain fluctuation, especially has the greater advantage in the amplitude consistency index debugging of the multiple TR assemblies.

The invention relates to an adapter card from PCI (Peripheral Component Interconnect) Express X1 to CPCI (Compact Peripheral Component Interconnect) Express X1, which can be used for converting a PCI Express X1 slot in a commercial and industrial control desk computer into a CPCI Express X1 slot meeting a PICMG (PCI Industrial Computer Manufacturers Group) EXP.0R1.0 standard so that a CPCI Express X1 interface card (expansion card) meeting the PICMG EXP.0R1.0 standard can be applied, debugged and tested in the PCI Express X1 slot in a common commercial and industrial control desk computer. The adapter card comprises an impedance control circuit board, a PCI Express interface, a CPCI Express signal socket, a double-row hole socket, an adapting circuit board, a connecting block, a bending double-row plug, a CPCI Express power supply socket and a baffle plate. The invention has the advantages and effects of not influencing the quality and effect of signals in the PCI Express X1 and the CPCI Express X1, expanding the application of the traditional PCI Express X1 slot to ensure that the traditional PCI Express X1 slot is compatible with the CPCI Express X1 interface card (expansion card), greatly reducing the difficulty and the cost of the development of the CPCI Express X1 interface card (expansion card) and having simple structure and convenient use.

The invention discloses an adapting card for peripheral component interface (PCI) Express X16 to compact peripheral component interconnect (CPCI) Express X16. The adapting card comprises an impedance control circuit board, an adapting circuit board, a PCI Express X16 interface, a CPCI Express signal socket, a CPCI Express power socket, a double-row hole socket, a bent pin double-row plug, a connecting block and a baffle plate, wherein the CPCI Express signal socket and the adapting circuit board are connected with the upper part of the impedance control circuit board; a PCI Express X16 interface is formed in the lower part of the impedance control circuit board; the bent pin double-row plug is arranged on the left middle part of the impedance control circuit board; and the CPCI Express power socket and the bent pin double-row plug are arranged on the adapting circuit board. The quality and the efficiency of a signal are not affected, the application range of the current PCI Express X16 slot is expanded, the difficulty and the cost for the development of a CPCI Express X16 interface card are greatly reduced, and the adapting card is simple in structure and convenient to use.

The invention provides a method and server for functional verification of a microprocessor. The method includes the steps that at least one random instruction, expected operating results corresponding to all the random instructions and initialization data are generated; a bit stream file is generated according to original-register transmission-level RTL codes of the microprocessor; the bit stream file is loaded into a hardware simulation accelerator, and the at least one random instruction and the initialization data are loaded into a memory of a simulation microprocessor and a user-visible register, and the simulation microprocessor is formed in the mode that the microprocessor is burned into the hardware simulation accelerator; the hardware simulation accelerator is controlled to operate the at least one random instruction; the function of the microprocessor is verified according to the operating result of the at least one random instruction through the hardware simulation accelerator and the expected operating results corresponding to all the random instructions. By means of the method and server in the technical scheme, the accuracy and the debugging performance of functional verification of the microprocessor can be improved.

The invention discloses a multi-channel audio test device and a test method. The multi-channel audio test device comprises an equipment access module, a control module, an audio signal acquisition module, an audio output module, a storage module and a terminal access module; the audio signal acquisition module is used for acquiring a first audio signal when a to-be-tested device plays a first preset audio through the audio playing interface in a playing test stage; the audio output module is used for playing a second preset audio in an answering test stage, so that an audio acquisition interface of the to-be-tested device acquires a second audio signal; and the terminal access module is used for receiving a control instruction of the terminal to enter a playing test stage, an answering test stage or a reading stage, and in the reading stage, the content stored by the storage module is read and output to the terminal.

The invention provides a method for realizing logging function and an intelligent network system. The intelligent network system records operation log of service flow according to log levels selected by a user, and presents log information to the user; and different log levels in the intelligent network system correspond to the log information with different detail levels and / or different emphasized contents. The intelligent network system can present the log information with the different detail levels and / or different emphasized contents according to different log levels, ensures system performance, simultaneously meets various requirements of users on acquisition of the log information, and improves the flexibility, debuggability and easy observation of log.

The invention relates to an adapter card for PCI (peripheral component interconnect ) Express X8 to CPCI (compact peripheral component interconnect ) Express X8. The adapter card comprises an impedance control circuit board, an adapting circuit board, a PCI Express X8 interface, a CPCI Express X8 signal socket, a CPCI Express X8 power supply socket, a double row socket, a curved needle double row plug, a connecting block and a baffle, wherein the upper edge of the impedance control circuit board is crimped with the CPCI Express X8 signal socket and the adapting circuit board; the lower edge is provided with the PCI Express X8 interface; the curved needle double row plug is arranged in an inclined left middle part of the impedance control circuit board; the CPCI Express X8 power supply socket and the curved needle double row plug are installed on the adapting circuit board; the connecting block is used for vertically fixing the impedance control circuit board and the adapting circuit board trough screws; and the baffle is connected with the impedance control circuit board and a computer case through screws. With the adoption of the adapting card for PCI Express X8 to CPCI Express X8 provided by the invention, the quality and function of signals in the PCI Express X8 and CPCI Express X8 are not affected, application of current PCI Express X8 slots is expanded, and the development difficulty and cost of a CPCI Express X8 interface card is greatly reduced; and the adapting card is simple in structure and convenient in use.

The invention relates to the field of air-ground robots, in particular to an air-ground dual-purpose hexapod robot. The robot is characterized in that a quad-rotor unmanned aerial vehicle is combined with a hexapod robot, and the robot specifically comprises a control cabin, a flying mechanism and a crawling mechanism. The control cabinet (1) and the flying mechanism (2) form the upper half part of the robot, and the crawling mechanism forms the lower half part of the robot. The unmanned aerial vehicle upper cover plate (13) and the vehicle arm (23) are located between the unmanned aerial vehicle upper cover plate (13) and the unmanned aerial vehicle lower cover plate (15) and connected through a folding mechanism A (21) and a folding mechanism B (22), and the motor pile (24) is located in the tail end of the vehicle arm (23) and internally provided with a rotor wing motor (26). And a crawling mechanism at the lower part of the robot realizes the movement of a foot structure through a hip joint steering engine (31), a knee joint steering engine (32) and an ankle joint steering engine (36). The problem that an existing robot is poor in land obstacle crossing ability is solved, and the robot can adapt to more complex geographical environments. And investigation and exploration tasks can be carried out in complex environments such as low-lying places and caves.

The invention provides a method for automatically identifying serial numbers of TR assemblies of a three-dimensional phased array radar antenna. The method comprises the following steps that (1) each TR assembly of the three-dimensional phased array radar antenna is connected with a serial number control line; (2) after being powered on, each TR assembly reads information of the serial number control line of itself, and serial number identification is conducted; (3) each TR assembly calls control words corresponding to the series number of itself so as to achieve beam control, receiving branch attenuation control and TR assembly self-inspection. The method has the prominent advantages that the TR assemblies of the three-dimensional phased array radar antenna interchange, debugging performance and working efficiency of a system can be improved, and maintainability of the system can be substantially improved.

The invention discloses an imaging light path system and belongs to the field of projection display. The imaging light path system comprises a light source, an illuminating light path and a light valve, wherein the illuminating light path is a two-section type subsystem and comprises a front section subsystem and a rear section subsystem, the front section subsystem is used for receiving illumination beam provided by the light source to output first parallel light and converging the first parallel light beam on the object space focal plane of the rear section subsystem, the rear section subsystem is used for converting the converged light beam into second parallel light beam and making the second light beam enter the light incidence face of the light valve at a preset angle. The imaging light path system can improve the tolerance and debugging properties of the system and facilitates adjustment of imaging quality.

The invention discloses a continuous reference line decision-making method and device, and the method comprises the steps: determining the semantic information of a reference line, and enabling the determined semantic information to comprise a first semantic information group for intention decision-making and a second semantic information group for direction decision-making; determining a reference line switching intention according to the first semantic information group; selecting an optimal reference line according to the reference line switching intention and the second semantic information group of each reference line; and determining a target reference line according to the selected optimal reference line. According to the scheme, the reference line decision is performed by adopting the semantic information determined for the reference line, so that the reasonability and reliability of the decision result can be ensured; and part of semantic information is used for decision analysis in each stage of decision making, so that the decision making process is clear, visual and interpretable, evaluation parameters, namely the semantic information, of decision analysis can be flexibly adjusted according to requirements, and the debuggeability and expandability of reference line cost evaluation are improved.

The invention relates to an embedded system for real-time detecting memory, and relative method for real-time detecting memory and picking up the memory cross mistake, wherein said method comprises: starting one real-tie memory detecting proxy mission module, and initializing the memory detection; receiving background user instruction, and setting memory detecting point; then transmitting said user instructions to the real-time memory detecting proxy mission module; and when the trigger conditions are met, adjusting abnormal interruption.

The invention relates to a double-break-point medium voltage magnetic retention relay. The relay comprises a cover shell, wherein the cover shell is provided with a coil combination, an armature combination and a contact system, the coil combination comprises a yoke iron, a magnet steel, a coil, an iron core and a magnet conductor, the armature combination comprises an armature and a movable contact piece, the armature is positioned below the magnet steel, movable contacts are arranged at both ends of the movable contact piece, and the movable contacts at both ends of the movable contact piececorrespond to the static contacts of the contact system; The coil is composed of two groups of coils with opposite winding directions. Firstly, one group of coils is energized, and the coil drives the armature to rotate around the shaft and drives the movable contact piece to rotate around the shaft, and is connected with the static contact point on one side of the contact system. The other set of coils is energized, and the coils drive the armature to rotate in the opposite direction about the axis, and drive the movable contact piece to rotate in the opposite direction about the axis, and are connected with the static contact on the other side of the contact system. The invention realizes the breaking contact between the contact system and the movable contact piece, and obtains sufficient clearance for cutting off the load in a limited space.

The invention discloses a dielectric filter unit and a dielectric filter. the dielectric filter unit comprises a first dielectric resonant cavity and a second dielectric resonant cavity, and the upper end face or the lower end face of the first dielectric resonant cavity is provided with a first frequency hole; the second dielectric resonant cavity is connected with the first dielectric resonant cavity, a second frequency hole is formed in the upper end face or the lower end face of the second dielectric resonant cavity, a coupling groove is formed in the joint of the first dielectric resonant cavity and the second dielectric resonant cavity, and a third frequency hole is further formed in the joint of the first dielectric resonant cavity and the second dielectric resonant cavity. And the third frequency hole is matched with the coupling groove, so that a third resonant mode is excited in the double-cavity structure, and the dielectric filter completes realization of three transmission modes under the condition that only the physical forms and the volume sizes of the two cavities are used, thereby achieving the performance of a third-order filter, generating an out-of-band transmission zero point at the same time, and having relatively high debuggeability and producibility.

The invention relates to the technical field of microstrip patch antennas. Particularly, the invention relates to a circularly polarized microstrip antenna with a director oscillator. The antenna comprises a microwave dielectric substrate, a metal patch assembly is fixed on the top surface of the microwave dielectric substrate; the metal patch assembly comprises a corner-cut inner metal patch anda peripheral metal patch, one side of the corner-cut inner metal patch is connected with an allocation branch and a feed probe, a metal cylinder is arranged in a through hole in the middle of the corner-cut inner metal patch, and the top end of the metal cylinder is connected with a plurality of height adjusting columns. The circularly polarized microstrip antenna with the director oscillator canplay a role in directing electric wave signals, and the centrality and stability of the antenna for receiving the electric wave signals are improved; meanwhile, the radiation characteristics of the microstrip antenna can be allocated in a small range after a PCB is processed, so that the antenna meets the requirements of specific indexes, and the debugging performance of an antenna product is improved; in addition, during mass production, the rejection rate of products can be reduced through a blending measure, so that the production cost is reduced.

The invention discloses an integrated intelligent operation device embedded into a Linux operating system. The integrated intelligent operation device comprises a driving operation device and a Linux operating system installation method, and the driving operation device comprises a bus order access module, an equipment bus adaptation module, an equipment management module and a product use module; and the bus order access module is located in the kernel of the Linux operating system, and the equipment bus adaptation module, the equipment management module and the product use module are located in a user mode of the Linux operating system. After the method for ensuring the normal startup of the Linux system is executed, when a file system on a hard disk is damaged, the system can be automatically recovered to be normally started without manual participation, so that the normal startup of an operating system can be ensured, and finally, the device driver maintainability, debuggeability and stability of the Linux operating system can be improved.

The invention relates to the technical field of microstrip patch antennas. Particularly, the invention relates to a dual-polarized microstrip antenna with a guide structure. The antenna comprises a microwave dielectric substrate, a metal patch assembly is fixed on the top surface of the microwave dielectric substrate; the metal patch assembly comprises a square inner metal patch and a peripheral metal patch, each of two sides of the square inner metal patch is connected with a deploying branch and a feed probe, a metal cylinder is arranged in a through hole in the middle of the square inner metal patch, and the top end of the metal cylinder is connected with a plurality of height adjusting columns. The dual-polarized microstrip antenna with the guiding structure can play a role in guidingan electric wave signal, so that the stability of receiving the electric wave signal by the antenna is improved; meanwhile, the radiation characteristics of the microstrip antenna can be allocated ina small range after a PCB is processed, so that the antenna meets the requirements of specific indexes, and the debugging performance of an antenna product is improved; and in addition, during large-batch production, the rejection rate of products can be reduced through the blending measure, and therefore the production cost is reduced.

The invention provides a method for automatically identifying serial numbers of TR assemblies of a three-dimensional phased array radar antenna. The method comprises the following steps that (1) each TR assembly of the three-dimensional phased array radar antenna is connected with a serial number control line; (2) after being powered on, each TR assembly reads information of the serial number control line of itself, and serial number identification is conducted; (3) each TR assembly calls control words corresponding to the series number of itself so as to achieve beam control, receiving branch attenuation control and TR assembly self-inspection. The method has the prominent advantages that the TR assemblies of the three-dimensional phased array radar antenna interchange, debugging performance and working efficiency of a system can be improved, and maintainability of the system can be substantially improved.

The present invention provides an on-chip debug and diagnostic method, a device and a chip. The method comprises the steps of monitoring the interrupt trigger information; generating a stop clock signal, a freeze signal and an interrupt trigger flag based on the interrupt trigger information; according to the stop clock signal, closing a functional clock; according to the freeze signal, freezing the state of a non-debug module port; upon monitoring the interrupt trigger flag, recording the state of an internal trigger and the internal state of a memory; after the recording is completed, recovering the function of the clock. Based on the on-chip debug and diagnostic method, the device and the chip, the functional clock can be automatically closed when the chip goes wrong, and the operation of a processor is paused. Meanwhile, the debug and diagnostic function is triggered automatically, so that the internal state of the chip can be quickly and accurately acquired. The debugging capability of the chip is effectively improved. therefore, the fault diagnosis is more rapid and the fault location is more accurate.

The invention discloses an imaging light path system and belongs to the field of projection display. The imaging light path system comprises a light source, an illuminating light path and a light valve, wherein the illuminating light path is a two-section type subsystem and comprises a front section subsystem and a rear section subsystem, the front section subsystem is used for receiving illumination beam provided by the light source to output first parallel light and converging the first parallel light beam on the object space focal plane of the rear section subsystem, the rear section subsystem is used for converting the converged light beam into second parallel light beam and making the second light beam enter the light incidence face of the light valve at a preset angle. The imaging light path system can improve the tolerance and debugging properties of the system and facilitates adjustment of imaging quality.

The invention relates to an adapter card for PCI (peripheral component interconnect ) Express X8 to CPCI (compact peripheral component interconnect ) Express X8. The adapter card comprises an impedance control circuit board, an adapting circuit board, a PCI Express X8 interface, a CPCI Express X8 signal socket, a CPCI Express X8 power supply socket, a double row socket, a curved needle double row plug, a connecting block and a baffle, wherein the upper edge of the impedance control circuit board is crimped with the CPCI Express X8 signal socket and the adapting circuit board; the lower edge is provided with the PCI Express X8 interface; the curved needle double row plug is arranged in an inclined left middle part of the impedance control circuit board; the CPCI Express X8 power supply socket and the curved needle double row plug are installed on the adapting circuit board; the connecting block is used for vertically fixing the impedance control circuit board and the adapting circuit board trough screws; and the baffle is connected with the impedance control circuit board and a computer case through screws. With the adoption of the adapting card for PCI Express X8 to CPCI Express X8 provided by the invention, the quality and function of signals in the PCI Express X8 and CPCI Express X8 are not affected, application of current PCI Express X8 slots is expanded, and the development difficulty and cost of a CPCI Express X8 interface card is greatly reduced; and the adapting card is simple in structure and convenient in use.

The present invention provides a temperature compensation equalization circuit of a TR assembly. The temperature compensation equalization circuit comprises a temperature compensation circuit and an equalization circuit, and the temperature compensation circuit adopts a PIN diode core and a DC bias circuit to realize a temperature compensation function. The DC bias circuit is formed by connecting a fixed resistor and a thermistor in series, the equalization circuit comprises the equalization resistors realized by a micro-strip open circuit stud and a lumped resistor on an open circuit transmission line, the equalization resistors are realized by the gold plated alumina ceramic substrates and the TaN resistive films, and the short circuit state of the two equalization resistors is realized by a gold wire welding technology. The temperature compensation equalization circuit can be applied to the ultra wide band TR assembly better, solves the problem that the ultra wide band TR assembly is large in gain fluctuation within the frequency bands and large in high-low temperature gain fluctuation, especially has the greater advantage in the amplitude consistency index debugging of the multiple TR assemblies.

The present invention discloses a method of combined state machine, the state machine includes sub-step structure analysis, sub state machine step of determining equivalence, the sub state machine extraction rule determination step, the step of converting the equivalent sub state machine and a sub state machine stitching step.And a state machine combined apparatus employing the method.The method and apparatus of the present invention can be dynamically configured when the pipeline, the pipeline will be used to describe the various pipeline stages to reduce the state machine configuration program consists of several to one, reduce the complexity of the control circuit and the circuit configuration can assist programmers still write state machine in accordance with the configuration program sub state machine, and the configuration program to obtain a combined state machine.

The invention discloses a PCIe-based hot-plug control method, which includes: a hot-plug management module detects whether a target module can respond to a hot-plug signal; if so, the hot-plug management module is located between the target module and a termination point. Act as a signal intermediary to realize the hot-plug power-on process; if not, the hot-plug management module sends an analog signal to the endpoint, where the analog signal is used to simulate the working signal sent by the target module to realize the hot-plug power-on process The embodiment of the present application also provides a hot-plug management module and a storage medium, which can use the hot-plug management module as a signal intermediary between the target module and the termination point to manage signal interaction in a unified manner when the system is working normally. During normal operation, an analog signal is generated to realize hot swapping, which simplifies the problem analysis workload in the process of debugging the system and improves the overall debuggability of the system.

The invention provides a two-channel wireless sensor node auxiliary debugging device, used for solving the problem that debugging information generated by a wireless sensor node at work cannot be transmitted and collected. The device comprises a wireless communication unit, a processor unit, a power supply unit, an electric quantity detection unit, the wireless sensor node and a debugging detection unit, the input end of the electric quantity detection unit is connected with the wireless sensor node while the output end of the same is connected with the processor unit, used for detecting voltage and current signals of the wireless sensor node, and an electric quantity signal of a battery of the wireless sensor node; the debugging detection unit is connected with the wireless sensor node and the processor, used for detecting the debugging information of the wireless sensor node; the wireless communication unit is connected with the processor unit, used for sending the collected debugging information, current and voltage information and battery electric quantity information of the wireless sensor node out; and the power supply unit is used for providing power to the processor unit. The device has the advantages of high debugging efficiency and low cost.