40results about How to "Improve debuggability" patented technology

The invention relates to an adapter card from PCI (Peripheral Component Interconnect) Express X1 to CPCI (Compact Peripheral Component Interconnect) Express X1, which can be used for converting a PCI Express X1 slot in a commercial and industrial control desk computer into a CPCI Express X1 slot meeting a PICMG (PCI Industrial Computer Manufacturers Group) EXP.0R1.0 standard so that a CPCI Express X1 interface card (expansion card) meeting the PICMG EXP.0R1.0 standard can be applied, debugged and tested in the PCI Express X1 slot in a common commercial and industrial control desk computer. The adapter card comprises an impedance control circuit board, a PCI Express interface, a CPCI Express signal socket, a double-row hole socket, an adapting circuit board, a connecting block, a bending double-row plug, a CPCI Express power supply socket and a baffle plate. The invention has the advantages and effects of not influencing the quality and effect of signals in the PCI Express X1 and the CPCI Express X1, expanding the application of the traditional PCI Express X1 slot to ensure that the traditional PCI Express X1 slot is compatible with the CPCI Express X1 interface card (expansion card), greatly reducing the difficulty and the cost of the development of the CPCI Express X1 interface card (expansion card) and having simple structure and convenient use.

The invention relates to an embedded system for real-time detecting memory, and relative method for real-time detecting memory and picking up the memory cross mistake, wherein said method comprises: starting one real-tie memory detecting proxy mission module, and initializing the memory detection; receiving background user instruction, and setting memory detecting point; then transmitting said user instructions to the real-time memory detecting proxy mission module; and when the trigger conditions are met, adjusting abnormal interruption.

The invention provides a method for automatically identifying serial numbers of TR assemblies of a three-dimensional phased array radar antenna. The method comprises the following steps that (1) each TR assembly of the three-dimensional phased array radar antenna is connected with a serial number control line; (2) after being powered on, each TR assembly reads information of the serial number control line of itself, and serial number identification is conducted; (3) each TR assembly calls control words corresponding to the series number of itself so as to achieve beam control, receiving branch attenuation control and TR assembly self-inspection. The method has the prominent advantages that the TR assemblies of the three-dimensional phased array radar antenna interchange, debugging performance and working efficiency of a system can be improved, and maintainability of the system can be substantially improved.

The present invention provides an on-chip debug and diagnostic method, a device and a chip. The method comprises the steps of monitoring the interrupt trigger information; generating a stop clock signal, a freeze signal and an interrupt trigger flag based on the interrupt trigger information; according to the stop clock signal, closing a functional clock; according to the freeze signal, freezing the state of a non-debug module port; upon monitoring the interrupt trigger flag, recording the state of an internal trigger and the internal state of a memory; after the recording is completed, recovering the function of the clock. Based on the on-chip debug and diagnostic method, the device and the chip, the functional clock can be automatically closed when the chip goes wrong, and the operation of a processor is paused. Meanwhile, the debug and diagnostic function is triggered automatically, so that the internal state of the chip can be quickly and accurately acquired. The debugging capability of the chip is effectively improved. therefore, the fault diagnosis is more rapid and the fault location is more accurate.

The invention discloses an imaging light path system and belongs to the field of projection display. The imaging light path system comprises a light source, an illuminating light path and a light valve, wherein the illuminating light path is a two-section type subsystem and comprises a front section subsystem and a rear section subsystem, the front section subsystem is used for receiving illumination beam provided by the light source to output first parallel light and converging the first parallel light beam on the object space focal plane of the rear section subsystem, the rear section subsystem is used for converting the converged light beam into second parallel light beam and making the second light beam enter the light incidence face of the light valve at a preset angle. The imaging light path system can improve the tolerance and debugging properties of the system and facilitates adjustment of imaging quality.

The invention relates to an adapter card for PCI (peripheral component interconnect ) Express X8 to CPCI (compact peripheral component interconnect ) Express X8. The adapter card comprises an impedance control circuit board, an adapting circuit board, a PCI Express X8 interface, a CPCI Express X8 signal socket, a CPCI Express X8 power supply socket, a double row socket, a curved needle double row plug, a connecting block and a baffle, wherein the upper edge of the impedance control circuit board is crimped with the CPCI Express X8 signal socket and the adapting circuit board; the lower edge is provided with the PCI Express X8 interface; the curved needle double row plug is arranged in an inclined left middle part of the impedance control circuit board; the CPCI Express X8 power supply socket and the curved needle double row plug are installed on the adapting circuit board; the connecting block is used for vertically fixing the impedance control circuit board and the adapting circuit board trough screws; and the baffle is connected with the impedance control circuit board and a computer case through screws. With the adoption of the adapting card for PCI Express X8 to CPCI Express X8 provided by the invention, the quality and function of signals in the PCI Express X8 and CPCI Express X8 are not affected, application of current PCI Express X8 slots is expanded, and the development difficulty and cost of a CPCI Express X8 interface card is greatly reduced; and the adapting card is simple in structure and convenient in use.

The present invention provides a temperature compensation equalization circuit of a TR assembly. The temperature compensation equalization circuit comprises a temperature compensation circuit and an equalization circuit, and the temperature compensation circuit adopts a PIN diode core and a DC bias circuit to realize a temperature compensation function. The DC bias circuit is formed by connecting a fixed resistor and a thermistor in series, the equalization circuit comprises the equalization resistors realized by a micro-strip open circuit stud and a lumped resistor on an open circuit transmission line, the equalization resistors are realized by the gold plated alumina ceramic substrates and the TaN resistive films, and the short circuit state of the two equalization resistors is realized by a gold wire welding technology. The temperature compensation equalization circuit can be applied to the ultra wide band TR assembly better, solves the problem that the ultra wide band TR assembly is large in gain fluctuation within the frequency bands and large in high-low temperature gain fluctuation, especially has the greater advantage in the amplitude consistency index debugging of the multiple TR assemblies.

The invention discloses an adapting card for peripheral component interface (PCI) Express X16 to compact peripheral component interconnect (CPCI) Express X16. The adapting card comprises an impedance control circuit board, an adapting circuit board, a PCI Express X16 interface, a CPCI Express signal socket, a CPCI Express power socket, a double-row hole socket, a bent pin double-row plug, a connecting block and a baffle plate, wherein the CPCI Express signal socket and the adapting circuit board are connected with the upper part of the impedance control circuit board; a PCI Express X16 interface is formed in the lower part of the impedance control circuit board; the bent pin double-row plug is arranged on the left middle part of the impedance control circuit board; and the CPCI Express power socket and the bent pin double-row plug are arranged on the adapting circuit board. The quality and the efficiency of a signal are not affected, the application range of the current PCI Express X16 slot is expanded, the difficulty and the cost for the development of a CPCI Express X16 interface card are greatly reduced, and the adapting card is simple in structure and convenient to use.

Disclosed is a state machine merging method. The merging method comprises a sub-state machine structure analysis step, a sub-state machine equivalency determining step, a sub-state machine extraction rule determining step, a sub-state machine equivalent transformation step, and a sub-state machine splicing step. Also disclosed is a state machine merging device using the method. According to the method and device of the present invention, when flow lines can be dynamically configured, the number of configuration programs for describing the state machines on each flow level on each flow line is reduced to one, so that the complexity of a control circuit and a configuration circuit is reduced, a programmer can be assisted in still compiling a configuration program of a state machine according to a sub-state machine, and a configuration program of a merged state machine is obtained.

The invention discloses a debugging method, comprising: the first network management module obtains the change value of the packet sent by the first chip and the change value of the packet received by the second chip, wherein, the first chip sends the packet to the second chip; if The first network management module judges that the change value of the packet sent by the first chip is greater than the change value of the packet received by the second chip, and judges that the link between the first chip and the second chip is blocked; the first network management module 1. The first chip and the second chip are set on the first server; the embodiment of the present application also provides a debugging system and a storage medium; the embodiment provided by the present invention monitors the sending and receiving of packets between the chips through the network management module , so as to judge the link blocking point between chips, and can quickly locate the problem when the overall link topology complexity in the system network increases, and improves the debuggability of the system.

The invention discloses a PCIe-based hot-plug control method, which includes: a hot-plug management module detects whether a target module can respond to a hot-plug signal; if so, the hot-plug management module is located between the target module and a termination point. Act as a signal intermediary to realize the hot-plug power-on process; if not, the hot-plug management module sends an analog signal to the endpoint, where the analog signal is used to simulate the working signal sent by the target module to realize the hot-plug power-on process The embodiment of the present application also provides a hot-plug management module and a storage medium, which can use the hot-plug management module as a signal intermediary between the target module and the termination point to manage signal interaction in a unified manner when the system is working normally. During normal operation, an analog signal is generated to realize hot swapping, which simplifies the problem analysis workload in the process of debugging the system and improves the overall debuggability of the system.

The invention provides a two-channel wireless sensor node auxiliary debugging device, used for solving the problem that debugging information generated by a wireless sensor node at work cannot be transmitted and collected. The device comprises a wireless communication unit, a processor unit, a power supply unit, an electric quantity detection unit, the wireless sensor node and a debugging detection unit, the input end of the electric quantity detection unit is connected with the wireless sensor node while the output end of the same is connected with the processor unit, used for detecting voltage and current signals of the wireless sensor node, and an electric quantity signal of a battery of the wireless sensor node; the debugging detection unit is connected with the wireless sensor node and the processor, used for detecting the debugging information of the wireless sensor node; the wireless communication unit is connected with the processor unit, used for sending the collected debugging information, current and voltage information and battery electric quantity information of the wireless sensor node out; and the power supply unit is used for providing power to the processor unit. The device has the advantages of high debugging efficiency and low cost.