46results about How to "Enhancing Capacitive Coupling" patented technology

An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it to the final target voltage. As the capacitive coupling in between the NAND word lines is a larger effect when the voltages are being lowered, this has the effect of damping out the voltage initially induced in the lower voltage word line by the rising voltages on the adjacent word lines, reducing the overall selection time.

A phased array antenna includes a substrate having a first surface, and a second surface adjacent thereto and defining an edge therebetween. A plurality of dipole antenna elements are on the first surface, and at least a portion of at least one dipole antenna element is on the second surface. Each dipole antenna element includes a medial feed portion and a pair of legs extending outwardly therefrom. Adjacent legs of adjacent dipole antenna elements on the first and second surfaces include respective spaced apart end portions having predetermined shapes and relative positioning for providing increased capacitive coupling between the adjacent dipole antenna elements.

Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

In a common mode choke coil, electrodes of input / output terminals are located on a bottom surface of a bottom layer. First linear conductors and second linear conductors are located on base material layers. A primary coil includes the first linear conductors and via hole conductors. A secondary coil includes the second linear conductors and via hole conductors. In a plan view as seen from a direction of winding axes of the primary coil and the secondary coil, as for a plurality of first linear conductors and second linear conductors which are adjacent in a plan direction, there are provided a first region in which the second linear conductors are located between the first linear conductors, and a second region in which the first conductors are located between the second linear conductors.

In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.