88results about How to "Ease of parallel processing" patented technology

A method and apparatus is provided for breaking down computing tasks within a larger application and distributing such tasks across a network of heterogeneous computers for simultaneous execution. The heterogeneous computers may be connected across a wide or local area network. The invention supports mobile agents that are self-migrating and can transport state information and stack trace information as they move from one host to another, continuing execution where the mobile agents may have left off. The invention includes a server component for providing an execution environment for the agents, in addition to sub-components which handle real-time collaboration between the mobile agents as well as facilities monitoring during execution. Additional components provide realistic thread migration for the mobile agents. Real-time stack trace information is stored as the computing tasks are executed, and if over-utilization of the computing host occurs, execution of the computing task can be halted and the computing task can be transferred to another computing hosts where execution can be seamlessly resumed using the stored, real-time state information and stack trace information.

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input / output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input / output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory / directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input / output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input / output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory / directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.

One embodiment of the present invention provides a switch that includes a transmission mechanism configured to transmit frames stored in a queue, and a queue management mechanism configured to store frames associated with the queue in a number of sub-queues which allow frames in different sub-queues to be retrieved independently, thereby facilitating parallel processing of the frames stored in the sub-queues.

A signal processor is configured to encode a signal in a hierarchy including multiple levels of quality. The signal processor produces a rendition of the signal for at least a first level of quality. The signal processor generates sets of reconstruction data specifying how to convert the rendition of the signal at the first level of quality into a rendition of the signal at a second (higher) level of quality in the hierarchy, potentially leveraging on available reference signals. According to one arrangement, the signal processor utilizes an entropy encoder to encode the reconstruction data. Based on probability distribution information for one or more symbols in each set of reconstruction data and based on probability distribution information and / or other encoding parameters inherited from previous levels of quality, the entropy encoder encodes the reconstruction data into an encoded value or bit string. Using the probability distribution information, an entropy decoder converts the encoded value or bit string back into the reconstruction data.

The invention discloses an unmanned aerial vehicle operating parameter automatic acquisition system and an automatic sensing method. The system comprises an operating parameter acquisition module array, a flight parameter acquisition module and a ground station. The method includes steps: acquiring geographic information of each operating parameter acquisition module; extracting operating parameter geographic information characteristics, programming an unmanned aerial vehicle sensing area to obtain a specific regional planar graphic equation of appropriate automatic sensing operation time; acquiring a flight path; pre-judging an unmanned aerial vehicle flight path to obtain a path equation; obtaining an intersection path on a canopy plane according to the path equation and the planar graphic equation, and taking a midpoint coordinate of the intersection path as a sampling target point; making sampling strategies, determining sampling time, acquiring effective operating parameters in a sampling time range, and sending to the ground station to realize processing. The unmanned aerial vehicle operating parameter automatic acquisition system and the automatic sensing method have advantages that simultaneous data acquisition and automatic determination of sampling time are realized, and errors caused by manual visual judgment under different flight conditions are avoided.

A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input / output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input / output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

Technology for relocating data stored in an end of life source storage drive that identifies individual destination drive extents corresponding to drive extents located in the source storage drive by selecting individual storage drives within a set of healthy storage drives in a group of storage drives in a round robin manner and identifying an individual destination drive extent from each selected storage drive. The corresponding destination drive extents replace the drive extents located in the source storage drive, and are used to store data copied from the drive extents located in the source storage drive. Data is copied in parallel from a set of multiple drive extents located in the source storage drive that is selected based on the current total input / output load determined for each storage drive in the set of healthy storage drives, and on the storage drives on which the corresponding destination drive extents are located.

The invention discloses a large-scale monitoring video stream converging method based on stream-oriented computation. The method comprises the following four steps: I, acquiring information about all cameras, and performing ranking according to importance degrees, required central processing unit (CPU) resources and Internet protocol (IP) addresses; II, acquiring information about Workers, and performing ranking according to CPU computing capabilities and IP addresses; III, selecting a properly-identified Worker computing container to serve as a startup position of a receiver according to a computing resource chain table; and IV, estimating resource computing capabilities of selected Workers. According to the method, the complexity in inputting data sources and the computing capabilities of the Workers are considered fully, and the video stream startup position is computed reasonably, so that data are executed locally as much as possible; the CPU utilization ratio of a system is increased; and the real-time computing capability of the system is enhanced. The method has a high practical value and a good application prospect in the technical field of parallel real-time processing of massive video data.

The present invention provides a functional block that executes video coding and video decoding based on H.264 / AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

An image processing apparatus includes a division unit configured to divide an input image into a plurality of subblocks subjected to quantization control a subblock quantization parameter calculation unit configured to calculate a quantization parameter of each of the subblocks, a basic block quantization parameter calculation unit configured to set a basic block including at least two subblocks and to calculate a quantization parameter of the basic block, a difference value calculation unit configured to calculate a difference value between the quantization parameter of the basic block and the quantization parameter of each subblock included in the basic block, and a difference value coding unit configured to code the difference value.

The invention belongs to the technical field of heterogeneous multi-processor computing, and particularly relates to a heterogeneous platform task scheduling method and system based on Q learning, which take all tasks as a Q learning state space, take a processor set as an action space, and wait for an allocated task as a current state. The method comprises the following steps: obtaining a task initial mapping scheme according to execution time required for mapping a task to an action space in Q learning; creating a genetic algorithm model, carrying out fitness evaluation on the task initial mapping scheme, setting individuals copied to the next generation of population in the genetic algorithm model according to fitness, carrying out crossover variation on reserved individuals, and determining new population optimization efficiency and a minimum threshold value; obtaining an approximately optimal solution mapped from a task to a processor in the model according to the genetic algorithm model; converting the model approximate optimal solution into ant colony information initial information distribution, and iteratively searching and outputting an optimal path through an ant colonyalgorithm according to the information distribution to obtain a task scheduling optimal scheme, so as to better improve the performance of the heterogeneous platform.

The invention relates to a data communication circuit arranged among a plurality of processors and adopting a data driving mechanism. The data communication circuit arranged among the plurality of processors and adopting the data driving mechanism comprises a crossbar switch matrix, four data stream memorizers and four match circuits. As shown in the figure, when data transfer is sent, a source CPU sends data to the crossbar switch matrix to achieve data transmission according to a preset protocol through a match circuit which is connected with the source CPU. When data are received, source data are transmitted to a corresponding output port of the crossbar switch matrix after the source data pass through the crossbar switch matrix to carry out path selection, the output data enter a data flow memory (DFM), and function numbers and the data are extracted and are transmitted to corresponding goal CPUs after completeness detection of the DFM is carried out on the data. The data communication circuit arranged among the plurality of processors and adopting the data driving mechanism can well solve the problem of a communication bottleneck which appears in a multi-core structure.