45results about How to "Data Retention Time Enhancement" patented technology

Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region. A field oxide layer is formed on the substrate around the active region in such a manner that it has a surface lower than the upper surface of the active region including the groove. A pair of gates are placed along one and the other ends of groove across the upper surface of the active region while overlapping the stepped portion of the active region. The transistor has the structure of a step-gated asymmetry transistor when seen in a sectional view taken in a first direction, as well as that of a fin transistor when seen in a sectional view taken in a second direction, which is perpendicular to the first direction. The transistor having such a structure can secure improved data retention time of the step-gated asymmetry transistor and excellent current driving properties of the fin transistor and is applicable not only to a logic device, but also to a memory device (for example, DRAM) requiring low-power and high-speed properties.

In a memory device including a dielectric multilayer structure, and a method of fabricating the same, the memory device includes a semiconductor substrate, a first impurity region and a second impurity region spaced apart from each other in the semiconductor substrate, and a gate structure formed on the semiconductor substrate and contacting the first impurity region and the second impurity region, the gate structure including a tunneling oxide layer on the semiconductor substrate, a charge storage layer on the tunneling oxide layer, an insulating layer on the charge storage layer, the insulating layer including at least two dielectric layers, and a gate electrode layer on the insulating layer.

The invention relates to a tube-like phase-change memory single structure and making method, the phase-change memory single structure comprises a top electrode, a bottom electrode and a memory part. The single structure has basic characters that: phase-change material distributes at lateral wall of a hole, the phase-change is implemented in the hole in reading and writing operation through heating own by using small sectional area and big resistance of the phase-change material, and tubular is formed at two ends of ring phase-change material through adding phase-change material insulating layer as closure, thus improving use efficiency of heat in the reading and writing operation, the memory part is a tubular structure enclosed by the phase-change material up and down, and is filled with metal, insulation materials or high resistivity material. The memory structure of the invention can reduce operating current, and has small-power, high heat utilization ratio and good data retention performance, and the invention can improve the consistency of resistance value of device of chip.

Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide / nitride / oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source / drain regions formed in the fin active region on both sides of the second gate electrode.

Memory devices and / or methods of storing memory data bits may be provided. A memory device may include a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and / or methods, it may be possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.

A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

Memory devices and methods of manufacturing the same are provided. Memory devices may include a substrate, a source region and a drain region and a gate structure. The gate structure may be in contact with the source and drain regions, and may include a barrier layer. The barrier layer may be formed of at least two layers. The at least two layers may have different bandgap energies.

A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.

A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

A semiconductor device includes a sense-amplifier driving device. The sense-amplifier driving device includes a sense-amplifier driver configured to provide a first pull-up voltage and a first pull-down voltage to a pull-up power line and a pull-down power line, respectively, during a first over-driving time period, provide the second pull-up voltage and the first pull-down voltage to the pull-up power line and the pull-down power line, respectively, during an active time period, and provide a third pull-up voltage and a second pull-down voltage to the pull-up power line and the pull-down power line, respectively, during a second over-driving time period, and a drive-signal generator configured to generate a plurality of drive signals, which is selectively activated during the first over-driving time period, the active time period, and the second over-driving time period, to control an operation of the sense-amplifier driver.

In one embodiment, a computer-implemented method of conserving storage space in a network recorder includes receiving a computer packet including a header and payload data; estimating entropy of the payload data in the computer packet; determining if storage of the computer packet is of value or not based on the header of the computer packet; and storing all or a portion of the computer packet into a storage device based on the estimated entropy and the value determination.

In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner that a write or read access to the weak regular memory cell is simultaneously also effected for a redundant memory cell in order to jointly read from, or write to, the weak regular memory cell and the redundant memory cell.

Disclosed is a semiconductor memory device including: a sense amplifier capable of sensing and amplifying data loaded on a data-line pair based on a pull-up driving voltage and a pull-down driving voltage; a pull-up driving unit capable of supplying a first voltage as the pull-up driving voltage for first and third active sections of an active mode, and supplying a second voltage having a voltage level lower than the first voltage as the pull-up driving voltage for a second active section of the active mode, between the first and third active sections of the active mode; and a pull-down driving unit capable of supplying a third voltage as the pull-down driving voltage for the first to third active sections of the active mode and for an initial section of a precharge mode after the active mode.

A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.

A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

The invention relates to a signal establishing time control circuit and a dynamic storage based on the same. The signal establishing time control circuit comprises a first delay unit, a second delay unit and a multiplexer, wherein a selected word line signal wlmimic is divided into two paths by virtue of the first delay unit, the first path directly outputs a signal SA_en1, the second path outputs a signal SA_en2 by virtue of the second delay unit, the multiplexer outputs sense amplifier enabling signals by selecting the signal SA_en1 and the signal SA_en2, and the gating of the multiplexer is controlled by virtue of signal refresh. According to the signal establishing time control circuit, the technical problem of short storage retention time when same signal establishing time is adopted during activation operation and refresh operation of an existing dynamic storage is solved, and the data retention time of the dynamic storage is effectively prolonged.