87results about How to "Avoid contact failure" patented technology

An electronic cigarette includes a mouthpiece, an atomizer assembly, a first connecting assembly, a second connecting assembly, and a power assembly. The atomizer assembly is received in the first housing of the mouthpiece, which includes a liquid reservoir and a heating element. The first connecting assembly includes a first conductive tube, a second conductive tube, and a first sleeve. The first sleeve includes an insulation tube, a convex ring, and a connecting portion. The insulation tube is disposed between the first conductive tube and the second conductive tube; the convex ring is sleeved on the second conductive tube and fixed to the first housing; the connecting portion extends through the second conductive tube and interconnects the insulation tube and the convex ring. The second connecting assembly includes a second sleeve and a flexible conductive ring. The power assembly includes a second housing fixed to the first housing and a battery.

A MIS transistor includes a gate electrode portion, insulating sidewalls formed on side surfaces of the gate electrode portion, source / drain regions and a stress film formed so as to cover the gate electrode portion and the source / drain regions. A height of an upper surface of the gate electrode portion is smaller than a height of an upper edge of each of the insulating sidewalls. A thickness of first part of the stress film located on the gate electrode portion is larger than a thickness of second part of the stress film located on the source / drain regions.

There is disclosed a wiringboard comprising a core substrate 110, a build-up layer 130a formed on at least one side of main surfaces the core substrate, wherein a cavity 120 for accommodating a chip-type decoupling capacitor 121 is formed in the build-up layer 130a. The capacitor 121 includes electrode terminals on an upper surface thereof that are directly connected to a semiconductor component, and electrode terminals on a back surface of the capacitor 121 is connected to a wiring conductor layer 132a on a bottom surface of the cavity 120. This structure enables decoupling capacitor and the semiconductor component 260 to be connected with low resistance and low inductance.

Disclosed are a display device and a method of manufacturing the same. In the disclosed display device, a pad cover electrode disposed on a pad area comes into contact with an upper surface and a side surface of a pad electrode since a planarization layer is disposed on an active area excluding the pad area, which may prevent contact failure between the pad cover electrode and a conductive ball. In addition, in the display device, a first electrode, which is connected to a thin film transistor via a pixel connection electrode, is formed via the same mask process as the planarization layer so that it has a line width similar to that of the planarization layer and overlaps the planarization layer, which may simplify a structure and a manufacturing process.

According to the present invention, there is provided a card adapter which is capable of preventing contact failure between a cover member and a ground terminal caused by the floating of the cover member when a card is inserted into a card inserting portion. A contacting surface 40 facing a back-end surface 1b of the card inserting portion 1a is provided on the ground terminal 12. A ground contacting portion 41 comprising a contacting portion 41a brought into contact with the contacting surface 40, a plate spring portion 41b extending in a widthwise direction of the card inserting portion 1a and bent in a lengthwise direction of the card inserting portion 1a, and a cantilever supporting portion 41c for supporting the plate spring portion 41b in a cantilever manner is formed in a bent portion 4a provided in a front-end portion of the cover member 4. In addition, in a lengthwise direction of the card inserting portion 1a, the contacting portion 41a of the ground contacting portion 41 is pressed against the contacting surface 40 of the ground terminal 12 to be brought into contact with each other through the elastic force of the plate spring portion 41b.

There is disclosed a wiring board comprising a core substrate 110, a build-up layer 130a formed on at least one side of main surfaces the core substrate, wherein a cavity 120 for accommodating a chip-type decoupling capacitor 121 is formed in the build-up layer 130a. The capacitor 121 includes electrode terminals on an upper surface thereof that are directly connected to a semiconductor component, and electrode terminals on a back surface of the capacitor 121 is connected to a wiring conductor layer 132a on a bottom surface of the cavity 120. This structure enables decoupling capacitor and the semiconductor component 260 to be connected with low resistance and low inductance.

A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a stack structure including conductive layers stacked in a step shape, a first interlayer insulating layer formed over the stack structure, the first interlayer insulating layer including contact holes with a uniform depth, which expose the conductive layers, lower contact plugs formed in the contact holes, the lower contact plugs being respectively contacted with the conductive layers, and lower contact pads respectively connected to the contact plugs.

A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.

In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact spacer on internal walls of the contact hole, a first contact plug connected to the contact pad exposed by the contact hole having the contact spacer on the internal walls thereof, the first contact plug partially filling the contact hole, a metal silicide layer on a surface of the first contact plug, and a second contact plug on the metal silicide layer and partially filling the remaining portion of the contact hole.

After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is formed on the recessed plug and on the insulation layer. A lower portion of the metal wiring structure, formed within the contact hole, prevents damage to the recessed plug during an etching process for forming the metal wiring structure. Therefore, the recessed plug may be formed without damage thereof even if an alignment error occurs between an etching mask and the recessed plug during metal wiring structure formation.

A semiconductor device includes a semiconductor substrate having a resistor region, an isolation layer disposed in the resistor region, the isolation layer defining active regions, first conductive layer patterns disposed on the active regions, a second conductive layer pattern covering the first conductive layer patterns and disposed on the isolation layer, the second conductive layer pattern and the first conductive layer patterns constituting a load resistor pattern, an upper insulating layer disposed over the load resistor pattern, and resistor contact plugs disposed over the active regions, the resistor contact plugs penetrating the upper insulating layer to contact the load resistor pattern.

A connector C to be mounted on a case of a device includes a coated wire 10 formed such that a core 11 is coated with an insulation coating 12, a terminal fitting 20 to be fit and connected to a mating terminal, a flexible conductor 15 interposed between the terminal fitting 20 and an end of the coated wire 10, and a housing 30 made of synthetic resin and accommodating the terminal fitting 20 together with the flexible conductor 15. The core 11 of the coated wire 10 is provided with a core fixing portion 25 integrated with the core 11 and the core fixing portion 25 is embedded in the housing 30 by molding.