312 results about "Transceiver chip" patented technology

An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Apparatus and methods for rack level pre-installed interconnect for enabling cableless server, storage, and networking deployment. Plastic cable waveguides are configured to couple millimeter-wave radio frequency (RF) signals between two or more Extremely High Frequency (EHF) transceiver chips, thus supporting millimeter-wave wireless communication links enabling components in the separate chassis to communicate without requiring wire or optical cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network / switch chassis. A plurality of plastic cable waveguide may be coupled to applicable support / mounting members, which in turn are mounted to a rack and / or top-of-rack switches. This enables the plastic cable waveguides to be pre-installed at the rack level, and further enables racks to be installed and replaced without requiring further cabling for the supported communication links. The communication links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.

Multi-mode-multi-band direct conversion receiver with complex I and Q channel interference mitigation processing for cancellation of intermodulation products are described. In one embodiment, a method comprising over sampling of the entire receiver passband to acquire the IMP source signals that can generate IMPs within the SOI, using these signals to generate a coherent complex I-Q channel estimates of the interference and (after phase and amplitude adjustment) using these estimates to cancel the SOI inband IMPs in the I and Q channels independently and simultaneously in near real time, generating estimates of 2nd and 3rd order IMP products, adjusting the phase and amplitude of the estimates and using the estimates to cancel the SOI inband IMPs on the I ad Q channels independently and simultaneously in real time or very near real time, sampling of the transmitter feed thru signal and blocking signals and computing the cross modulation products estimate and adjusting the phase and amplitude and using the estimate to cancel the SOI inband cross modulation products energy in real time or near real time in the I and Q channels of the receiver, using the cross modulation cancellation to cancel of the effects of the on chip transmitter feed thru to support building a single transceiver chip with full duplex operation with cancellation being done independently and simultaneously on the I and Q channels of the receiver, and creation of an estimate of the DC offset in the receiver and adjusting the amplitude of the DC offset in a near real time closed loop fashion to cancel the DC offset in the I and Q channels independently and simultaneously and adjusting the rate of update to match system parameters.

Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10−12.

An anti-metal radio frequency identification (RFID) tag and a manufacturing method thereof are described. The anti-metal RFID tag includes a substrate having a first surface and a second surface on an opposite side thereof; a planar integral antenna formed on the first surface of the substrate; a RFID transceiver chip (i.e., RFID chip) disposed on the surface of the substrate and coupled to a signal feed point of the planar integral antenna. The flexible planar integral antenna and substrate are folded and then fixed by a fixing mechanism to form an anti-metal RFID tag with a feed-in structure, a RFID transceiver chip, and a radiator on one side, and a ground plane on the opposite side. A spacer is further sandwiched in the center of the folded structure, which is helpful for improving the antenna gain of the anti-metal RFID tag.

A microcontroller radio card (2) for insertion into a first device, e.g., a camera (10) to allow for remote operation of a second device, e.g., a flashpack (22), utilizing the existing controls of the first device. The card includes a base (34) populated with various microelectronic devices for transmitting and or receiving RF or other signals used in the control and operation of the second device. A central processing unit (CPU) (41) translates signals received from the first device and controls the generation of corresponding signals to be transmitted to the second device in response to the signals received from the first device. Signals are transmitted to the second device via a transceiver chip (43).

An RF front-end architecture is operated in either a transmitting or a receiving mode. The RF front-end architecture comprises an antenna, an impedance match network, a balun and a transceiver chip. The transceiver chip comprises first and second transmit / receive (TR) switches, a transmitter, and a receiver. Because two TR switches are integrated into the chip, the printed circuit board area, BOM cost and pin count of the transceiver chip can be greatly reduced.

A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Methods and systems for processing data are disclosed herein and may include compressing audio information on-chip within a Bluetooth® transceiver chip utilizing an audio codec implemented within the Bluetooth® transceiver chip. The audio codec may be a low complexity sub-band codec (SBC). An audio stream with the audio information may be generated outside the Bluetooth® transceiver chip. The audio stream may be generated via an audio / video distribution transport protocol (AVDTP) external to the Bluetooth® transceiver chip. A data channel may be established by the Bluetooth® transceiver chip between a Bluetooth® enabled device and a peer Bluetooth® device, for communicating the established audio stream to the Bluetooth® transceiver chip for compression. The data channel may be established utilizing a logical link control and adaptation protocol (L2CAP) and / or an advanced audio distribution profile (A2DP).

The invention discloses a smart factory-based multi-function data acquisition device, acquisition system and method. The acquisition device comprises a microprocessor as well as a power supply module, a 485 transceiver chip, a 232 transceiver chip, an IO signal conversion circuit and two Ethernet protocol stack chips which are connected with the microprocessor, wherein the 485 transceiver chip and the 232 transceiver chip are respectively provided with an RS-485 Interface and an RS-232 interface which are used for connecting external devices and acquiring device data, the Ethernet protocol stack chips are provided with Ethernet interfaces and are used for connecting upper computers or other acquisition devices and transmitting data, and the IO signal conversion circuit is provided with an IO port and is used for connecting external devices, acquiring signals or controlling the devices. The data acquisition device can be configured to a master station mode or a slave station mode, and is flexible in interfacing, and therefore, the data acquisition device can read data of field devices and scattered acquisition points more economically, conveniently and efficiently and provide complete and accurate bottom data for the establishment of a smart factory.

The invention provides a multi-module terminal circuit and a multi-module terminal. The multi-module terminal circuit comprises n radio frequency transceiver chips, an antenna, a switch module and a front-end module, wherein the switch module is connected with the n radio frequency transceiver chips through a first uplink and a first downlink respectively, the front-end module is connected with the switch module through a second uplink and a second downlink respectively and is also connected with the antenna; signals transmitted by the n radio frequency transceiver chips are sent to the front-end module through the first uplink, or signals transmitted by the front-end module are received through the first downlink; after processing the signals transmitted by the switch module, the front-end module sends the processed signals to the antenna through the send uplink, or sends the signals received from the antenna to the switch module through the second downlink; and 'n' is a natural number larger than or equal to 2. The multi-module terminal circuit and the multi-module terminal provided by the invention have the advantages of saved cost and reduced area occupied by the multi-module terminal circuit.

A method, apparatus, system, and computer program products provides personal alert and tracking capabilities using one or more nodes. Each node includes radio transceiver chips operating at different frequency ranges, a power amplifier, sensors, a display, and embedded software. The chips enable the node to operate as either a mobile sensor node or a relay base station node while providing a long distance relay link between nodes. The power amplifier enables a line-of-sight communication between the one or more nodes. The sensors provide a GPS signal, temperature, and accelerometer information (used to trigger an alert condition). The embedded software captures and processes the sensor information, provides a multi-hop packet routing protocol to relay the sensor information to and receive alert information from a command center, and to display the alert information on the display.

The invention discloses a PHS mobile phone which comprises an antenna, a front end filter, an antenna switch, a radio frequency power amplifier, a radio frequency transceiver chip, a baseband chip, a memory and a peripheral device. The antenna, the front end filter, the antenna switch, the radio frequency power amplifier, the radio frequency transceiver chip and the baseband chip are connected in turn, and the baseband chip is further connected with the memory and the peripheral device respectively. The invention further discloses a transmission power control method of the PHS mobile phone. The PHS mobile phone can adjust the transmission power of the PHS mobile phone at all times according to the strength range of received signals. The transmission power of the PHS mobile phone is increased in the weak signal area, and the transmission power of the PHS mobile phone is reduced in the stronger signal area.

In current applications, when a short distance wireless transceiver chip transmits and receives data, transmitting power and receiving power are fixed, usually in order to achieve the purpose of signal communication, the data are transmitted and received by utilization of maximum power / maximum gain, in actual applications, under most conditions, the data are not needed to be transmitted and received by utilization of the maximum power / maximum gain, and extremely large waste of power consumption is caused. The invention provides a method dynamically controlling the transmitting power and the receiving power of the transceiver chip, communication equipment and a communication system based on an RSSI, the transmitting power and the receiving power are further lowered according to the actual applications, the power consumption is reduced, and the service life of a battery is prolonged.

The present invention pertains to the field of the design technology of wireless communication system transceiver chip. The characteristics reside in that: the novel back-to-back series connected type MOS varactor adopting the digital signal control forms the main hypercap part of the numerical controlled LC oscillator, and the phase noise converted from the amplitude noise from the oscillator is reduced, and the restraining ability of the oscillator to the noise from the current source is improved, thus, the phase noise of the output signal of the oscillator is finally reduced. The method in the present invention, comparing with the prior method, can improve the performance of the on-piece CMOS oscillator and reduce the power consumption of the oscillator effectively, thus, the method is useful to the reduction of the manufacturing cost and power consumption of the receiver.

The invention discloses a dual-channel compact small from-factor pluggable circuit, which relates to an optical communication technology, in particular to an optical module circuit realizing photoelectric signal conversion in optical communication. The designing key points of the circuit are that: the circuit comprises an interface circuit, a microcontroller, a first bi-directional optical sub-assembly, a second bi-directional optical sub-assembly, a first integrated transceiver chip, a second integrated transceiver chip and a power starting circuit, wherein the first bi-directional optical sub-assembly and the first integrated transceiver chip form a first optical channel; the second bi-directional optical sub-assembly and the second integrated transceiver chip form a second optical channel; the electric signal output ends of the bi-directional optical sub-assemblies of each optical channel are connected with the electric signal receiving ends of the integrated transceiver chips of the same optical channel; and the interface circuit is used for realizing the communication of the microcontroller, signal interfaces of the two integrated transceiver chips and the power starting circuit with an upper computer. The dual-channel compact small from-factor pluggable circuit has the advantages of low cost, simple circuit structure and small size.

The invention provides a 400 Gbps hot-plug high-speed optical transceiver module which is suitable for the optical communication technical field. The 400 Gbps hot-plug high-speed optical transceiver module comprises an optical interface unit, a photoelectric transceiver unit and an electrical interface unit; the photoelectric transceiver unit is used for achieving the functions of photoelectric conversion and high-speed electrical signal processing through a photoelectric transceiver chip; the internal working process of the photoelectric transceiver chip comprises receiving an electrical signal input through the electrical interface unit by a transmitting terminal data clock recovery circuit, loading the electrical signal to a laser after the pretreatment through a driving circuit, converting the high-speed electrical signal into a high-speed optical signal through the laser, reusing the high-speed optical signal through a wavelength division multiplexer to be output, reusing the received optical signal into a 16-channel optical signal through a wavelength division demultiplexer to be transmitted to an optical detector and transmitting the 16-channel optical signal to a trans-impedance amplifier and a receiving terminal data clock recovery circuit after photoelectric conversion to be processed. According to the 400 Gbps hot-plug high-speed optical transceiver module, the factors such as the cost, the transmission loss, the chromatic dispersion and the size are considered to select different optical transceiver modules and accordingly the long-distance single-mode optical fiber transmission or the short-distance multimode transmission is implemented.

The invention provides a distributed communication-in-motion light shaped antenna which is composed of a plurality of distributed front ends (9), a distributed optical fiber signal network (6), a distributed low-frequency signal network (7) and a distributed grating sensor network (8). Each of the distributed front ends comprises a distributed antenna sub-array (1), an electro-optical / photoelectric conversion chip (3), a sub-array wave beam control system (4) and a grating sensor (5), which are electrically connected around a silicon-based integrated transceiver chip (2). Under command control of a centralized processing terminal (10), each distributed front end (9) can implement beam scanning and satellite signal alignment; and then the plurality of distributed front ends (9) implement beam forming and real-time satellite communication under command control of the centralized processing terminal (10). The technical problem that the existing communication-in-motion antenna is designed in an integrated mode in an aperture, is large in size and heavy, and is hard to match a flexible wing structure in stiffness is solved.

A system and method for a structure monitoring and locating a disturbance event is disclosed. The system includes a compact transceiver chip sending optical signals in three optical fibers that encompass the monitored structure appropriately. The system contains a sequence of loops, wherein the first and the second fiber forming the loop clockwise, while the third fiber is winded along the same loop counterclockwise. A set of two detectors registers the returning signals, and a time delay between those signals is calculated, which is indicative of the disturbance event location. The event location is determined with different sensitivity in different parts of the monitored structure depending on the density of fibers in these parts.

The invention discloses an indoor high precision personnel positioning system. The system comprises a label, a base station and a positioning engine, wherein the label comprises a casing, the casing is internally provided with a battery module, a first circuit board, a first antenna, a first UWB transceiver chip, a first single-chip microcomputer, a first USB connection female seat and a motion sensing chip, the base station is provided with a second antenna, a second circuit board, an external power supply port, an RJ45 network port, a second USB connection female seat, a second UWB transceiver chip, a second single-chip microcomputer and a serial port server, the positioning engine includes a positioning server, and positioning algorithm software is installed on the positioning server. The system is advantaged in that one-dimensional and two-dimensional positioning can be completed through simply selecting two base stations by the positioning algorithm, the system is suitable for specific environments such as data centers, through comparing signal intensity of the label at cabinet channels of the base station, label positioning base station group selection is made to be more accurate.

The invention discloses a rock burst prediction method. According to the method, a three-dimensional vibration-picking connecting sleeve (2) is fixedly connected between an electric coal drill (1) and a drilling rod (3), the three-dimensional vibration-picking connecting sleeve (2) is used for synchronously collecting three-dimensional vibration signals of the drilling rod in the drilling process, the vibration signals are wirelessly transmitted to a signal transceiver (6) for storage through a wireless radio frequency transceiver chip (5) on the three-dimensional vibration-picking connecting sleeve (2), a spectrum curve is output at an interval time T, the first 8 orders of master frequency of each spectrum curve are recorded, a changing curve of each order of master frequency along with the drilling depth or time is output, then the number of distortion points on the changing curve of each order of master frequency along with the drilling depth or time is used for predicting rock burst tendentiousness of a coal bed, and the amount of drilling cuttings and the vibration curves obtained in drilling are combined to predict rock burst comprehensively. By means of the method, impacting phenomena of drill sucking, drill clamping and drilling are digitalized, and accuracy of rock burst prediction is greatly improved.

The invention discloses a low-power-consumption remote wireless transmission system, comprising a main MCU, a plurality of branch MCUs and radio frequency chips corresponding to the MCUs. The main MCUand the corresponding radio frequency chip form a wireless transmission center node. The plurality of branch MCUs are connected with the corresponding radio frequency chips to form wireless transmission subnodes. The radio frequency chips correspondingly connected with the MCUs are wireless radio frequency transceiver chips based on a LoRa technology. A star network topology structure is employedbetween the center node and the subnodes. The center node and the subnodes are networked through adoption of a TDMA medium access layer protocol. The subnodes finish collecting data and send the datato the center node in corresponding time slots. The center node gathers the data and is connected with a host. The data is displayed by the host. The subnodes ensure the low power consumption of networking in an RTC clock automatic wakeup mode, and moreover, through matching of a frequency hopping communication technology, the same frequency interference problem of the wireless transmission system is reduced. According to the system, a demand of an Internet of things application for power consumption and distance is satisfied, and the system can be widely applied to smart city projects such as smart parking and intelligent meter reading.

A millimeter wave (MMW) transceiver module includes a microwave monolithic integrated circuit (MMIC) transceiver chip set that is surface mounted on a circuit board. The MMIC transceiver chip set includes a receiver MMIC chip package, a transmitter MMIC chip package, and a local oscillator (LO) multiplier MMIC chip package. Each MMIC chip package includes a base and a multilayer substrate board formed from layers of low temperature transfer tape. The multilayer substrate board has at least three layers and carries RF signals, DC signals, grounding and embedded passive components, including resistors and capacitors. At least one MMIC chip is received on the multilayer substrate board.