128results about How to "Reduce phase difference" patented technology

A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down control unit, in response to some of a plurality of global clock signals, a phase detection signal, and a power down signal, outputs an input clock signal to each of the global clock generator and the clock delay unit. During the power down mode, the clock delay unit is enabled to periodically carry out the locking operation whenever it receives the input clock signal. Therefore, a consumed power of the DLL can be decreased during the power down mode, and a phase difference between an external clock signal and an internal clock signal during the power down mode can be decreased by the periodical locking operation of the clock delay unit, so that the DLL can operate at a fast speed after the power down mode.

A method and an apparatus are provided for synchronizing clock signals in spatially distributed nodes in large, synchronous electronic, optical, optoelectronic or wireless systems, such as systems comprising arrays of microprocessors and memories, and telecommunication systems. The nodes comprise a master node and a plurality of slave nodes. The master node generates first and second identical pulse trains and propagates them to the slave nodes via a first and second propagation channels, respectively, so that a pair of pulses, one from each pulse train, arrive at each slave node substantially simultaneously, travelling in opposite directions. Each slave node generates a clock signal event in response to the substantially simultaneous arrival of each pair of pulses. The master node maintains the rate of the two pulse trains such that there are “pN” pulses in each propagation channel at any time, where “N” is the number of nodes and “p” is an integer. Adjustable delays are provided at each slave node, disposed in each propagation channel. When the pulses in the two channels do not arrive simultaneously, the slave node adjusts the delay units so as reduce differences in the arrival times of subsequent pairs of pulses. The delay units may comprise pre-delay units upstream of the detection point and post-delay unit downstream of the detection point, any increment in a pre-delay being compensated by an equal decrement in the post-delay in the same propagation channel.

The phase interpolator includes two adjustable delays 30 and 31, phase comparator 32 which detects a phase difference between a signal delayed by the adjustable delay 30 and a signal delayed by the adjustable delay 31, an integrator 33 which integrates the outputs of the phase comparator 32 and multipliers 34-1 and 34-2 which set a control voltage for the adjustable delays 30 and 31. The feedback loop comprising phase comparator 32 and integrator 33 controls a delay amount of the adjustable delay 30 thereby securing a phase relation between {ACK1, ACK2} and ICK to achieve a stable ICK phase.

Power is fed from a feeding coil L2 to a receiving coil L3 by magnetic resonance. A VCO alternately turns ON / OFF switching transistors Q1 and Q2 at a drive frequency fo, whereby AC current is fed to the feeding coil L2, and then the AC current is fed from the feeding coil L2 to the receiving coil L3. A phase detection circuit detects a phase difference between the current phase and voltage phase, and the VCO adjusts the drive frequency fo such that the phase difference becomes zero. In a current phase detection circuit and a voltage phase detection circuit, detection values of the current and voltage phases can be changed, respectively and intentionally.

Power is fed from a feeding coil L2 to a receiving coil L3 by magnetic resonance. A VCO 202 alternately turns ON / OFF switching transistors Q1 and Q2 at a drive frequency fo, whereby AC power is fed to the feeding coil L2, and then the AC power is fed from the feeding coil L2 to the receiving coil L3. A phase detection circuit 114 detects a phase difference between the current phase and voltage phase, and the VCO 202 adjusts the drive frequency fo such that the phase difference becomes zero. When load voltage is changed, the detected current phase value is adjusted with the result that the drive frequency fo is adjusted.

A control system for an electric machine, the control system including a position sensor and a drive controller. The drive controller generates one or more control signals for exciting a winding of the electric machine in response to edges of a signal output by the position sensor. The times at which the control signals are generated by the drive controller are corrected by a position-sensor offset that is fixed over an operating speed range of the electric machine.

A two-point frequency modulation apparatus is provided that reduces input timing difference and improves modulation accuracy. Two-point frequency modulation apparatus 10 has: PLL circuit 11; frequency division ratio generator 13 that generates the frequency division ratio in frequency divider 111 based on first digital baseband signal S1 and carrier signal; adder 114 that adds second digital baseband signal S2 to the output signal of loop filter 113; a delay index calculator (filter coefficient calculator 17) that calculates the delay index based on the magnitude of change in the amplitude of the output signal of adder 114; and a delay adjuster (digital filter 18) that shifts the phase of one of first digital baseband signal S1 and second digital baseband signal S2 according to the delay index so as to reduce the phase difference.