78 results about "Processor model" patented technology

An embodiment of the invention relates to an apparatus including a power semiconductor device and a processor coupled thereto. The processor is configured to provide a control signal to the power semiconductor device to regulate an output characteristic of the apparatus. The processor models an internal characteristic of the power semiconductor device and alters the control signal if the modeled internal characteristic crosses a threshold value. In an exemplary embodiment, the internal characteristic is a channel temperature of a MOSFET. A sensor such as a thermistor is coupled to or included within the processor to sense a parameter separate from the power semiconductor device, such as a processor temperature, and the processor is configured to adapt the modeled internal characteristic to the sensed parameter.

The invention provides an extensible embedded simulation test system which is formed through minimizing coupling degree between an operation interface and an underlying virtual machine and defining an excellent module design and is used for overcoming the disadvantage of insufficiency of embedded software testing caused by overdependence on target hardware in an embedded software testing process. The system comprises a user interface layer and a virtual machine simulation layer, wherein the user interface layer is a user interaction layer which is completely independent of other layers, and is called to interact with the underlying virtual machine only through command lines, and the virtual machine simulation layer is used for realizing the simulation of the target hardware. The system is applicable to virtual machine frameworks of a plurality of processors, establishes abstract embedded processor models, and provides an interface so as to integrate an upper software testing function.

A method and system for the automatic generation of user guides. Specifically, the method of the present invention includes accessing an abstract processor model of a processor, wherein said abstract processor model is represented using a hierarchical architecture description language (ADL). The abstract processor model includes a plurality of instructions arranged in a hierarchical structure. An internal representation of the abstract processor model is generated by flattening the abstract processor model. The flattening process generates a plurality of rules grouped by common convergent instructions. Each rule describes an instruction path through the hierarchical structure that converges at a corresponding convergent instruction. An instruction-set documentation is automatically generated from the plurality of rules, wherein the instruction-set documentation is arranged convergent instruction by convergent instruction.

An input motion acquiring unit acquires a motion trajectory of an object from an image recognizing unit. A dynamic modeling processor models a plurality of robot motion patterns stored in a robot motion pattern storage unit in a dynamic system form, and stores the modeled robot motion patterns into a robot-motion-pattern-model storage unit. A motion converting unit linearly transforms the plurality of robot motion dynamic models stored in the robot-motion-pattern-model storage unit into prediction motion trajectories. A motion comparing unit compares the input motion trajectory acquired by the motion acquiring unit with the prediction motion trajectories transformed by the motion converting unit. A robot motion selecting unit selects a robot motion pattern having the highest similarity from the robot motion pattern storage unit. The present invention is applicable to a robot apparatus.

The invention relates to a method for designing a specific instruction set processor, and the method can make the accuracy performance evaluation at the beginning of designing a chip, advance the test of a specific application, speed up the design process and reduce the re-design possibility which is because the performances of the chip can not achieve the requirements. The method establishes an LISA processor model at the early stage of the design, generates a corresponding software tool by the LISA model, builds up a virtual prototyping platform which is similar to the performances of real hardware on an ARM ESL, including a AHB bus model with precise cycle, an EMI model and an SDRAM model which are needed for designing the platform, searches out the performances under the different situations by repairing the models of the processor, obtains an optical software / hardware dividing method, directly verifies on the models and speeds up the design cycle of the processor.

Computing device, computer instructions and method for denoising marine seismic data recorded with first and second seismic sensors. The method includes receiving first seismic data recorded with the first sensor in a time-space domain; receiving second seismic data recorded with the second sensor in the time-space domain, calculating with a processor models of the first and second seismic data in a transform domain that is different from the time-space domain; calculating in the transform domain an energy related to a down-going energy based on the models of the first and second seismic data; determining a noise in the transform domain corresponding to the second seismic data based on the calculated energy; reverse transforming the noise from the transform domain into the time-space domain; and denoising the second seismic data by subtracting the noise in the time-space domain from the second seismic data.

Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model processing of a first processor model and the core model processing of a second processor model. The inter-core-model communication processing is performed such that the inter-core-model communication required for the simulation processing of a multi-processor model is performed in parallel with the core model processing.

A coherency algorithm for a multi processor environment to run on a single processor model is verified by: generating a reference model reflecting a private cache hierarchy of a single processor within the multi processor environment, stimulating the private cache hierarchy with simulated requests and / or cross invalidations from a core side and / or from a nest side, and augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, which are set based on interface events. Multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further, a single processor model and a computer program product can be employed to execute the method.

The invention relates to the field of set top boxes, in particular to a drive program starting method and a drive program starting system for a set top box. The method includes steps: S1, recognizing a processor model and a communication device model of the set top box; S2, acquiring a preset drive configuration file corresponding to the processor model to obtain a first drive configuration file; S3, acquiring a number of a first port for connection of a processor and a communication device, and writing the number of the first port into the first drive configuration file to obtain a second drive configuration file; S4, setting values of drive program path parameters of the second drive configuration file according to the communication device model to obtain a third drive configuration file; S5, starting a drive program corresponding to the communication device model according to the third drive configuration file. The universal method for automatically loading drive programs of different models of communication devices is provided for the set top boxes with different models of processers.

The invention discloses a signature calibration method and a terminal device. The signature calibration method includes the steps of obtaining hardware information of the terminal device in the state that a system is safely started, and conducting calibration to find out whether a system software package is legal or not through the terminal device according to N pieces of signature information in the system software package and the hardware information of the terminal device, wherein the hardware information of the terminal device includes at least one of the type of a processor of the terminal device, information of a manufacturer and the type of the device or any combination of the type of the processor of the terminal device, information of the manufacturer and the type of the device, the N pieces of signature information is generated according to original data of the system software package and different types of hardware information, and N is larger than or equal to 2. Due to the fact that the N pieces of signature information is generated according to the original data of the system software package and the different types of hardware information, the signature calibration method and the terminal device can adapt to safe starting of various types of hardware, and when the hardware information such as the type of the processor, the information of the manufacturer and the type of the device changes, normal use such as starting of the device, updating of the device and maintaining of the device can not be influenced.

A telecommunications network capacity planning system. The telecommunications network capacity planning system includes a telecommunications network including a telecommunications services provider, subscribers and a network coupling the telecommunications services provider and the subscribers for provisioning of the telecommunications services. A database system is used for collecting and storing data at the user-level associated with provisioning of telecommunication services over the telecommunications network. A processor is coupled to the database system. The processor models the telecommunications network by generating upward projections from the stored user-level data and transforms the modeling of the network to a visual display of capacity information and network parameters for manipulation to evaluate capacity planning scenarios.