CPU restraint forming and verifying method based on boundary condition and self detection random test

A technology of random testing and boundary conditions, applied in software testing/debugging, etc., can solve problems such as time-consuming and large re-testing time consumption, and achieve the effect of independent architecture, accelerated verification progress, and rapid discovery

Inactive Publication Date: 2005-10-19
TSINGHUA UNIV
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Problems solved by technology

This is a time-consuming process, especially in the later stage of the test, many test programs have been run, and each modification will cause a lot of time consumption for re-testing

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  • CPU restraint forming and verifying method based on boundary condition and self detection random test
  • CPU restraint forming and verifying method based on boundary condition and self detection random test
  • CPU restraint forming and verifying method based on boundary condition and self detection random test

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Embodiment Construction

[0070] The specific implementation mode of the CPU constraint generation verification method based on boundary conditions and self-checking random testing is as follows:

[0071] Two models are included in the random testing environment: architectural model and RTL model. The architecture model is the desired processor model, which is implemented using a C simulator and exists as a standard reference model. The RTL model is the model to be tested and verified. The purpose of random testing and verification is to test whether the RTL model is consistent with the architectural model.

[0072] Both the RTL model and the architecture model can output the processor state at each clock cycle, and by comparing the processor states of the two models, it is possible to judge whether the two models are consistent. If they are inconsistent, it means that there is an error in the RTL model. The goal of random testing is to achieve complete agreement between the RTL model and the archite...

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Abstract

The present invention belongs to the field of automatic computer verifying technology, and is the CPU restraint creating and verifying method based on boundary condition and random self test. The specific mode is one random test environment including system structure model and RTL model. The system structure model is expected processor model realized with C simulator and used as the standard reference model. The RTL model is one to be tested and verified, and the random test and verification aims at testing the consistency of the RTL model to the system structure model. Both the RTL model and the system structure model can output separate processor state in each clock period, and comparing the processor state of these two model can judge the consistency. The present invention has independent system structure, and can constitute new verifying platform easily to raise the verification speed and quality greatly.

Description

technical field [0001] The invention belongs to the technical field of computer automatic verification, in particular to a computer microprocessor random verification method. Background technique [0002] As the functions of the microprocessor become more and more powerful and the structure becomes more and more complex, the research and development of the microprocessor system structure has become a very complicated process, which requires that the functions And the results are strictly tested and verified. [0003] Microprocessor verification methods are generally divided into two categories: formal methods and simulation-based methods. The formal method is mainly through mathematical abstraction, using the transition of the state machine on the mathematical method to perform functional simulation and verification, to prove the correctness of the system in theory, and to ensure the correctness of the system with 100% accuracy. Due to the widespread use of high-complexity...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
Inventor 姚文斌张悠慧王惊雷
Owner TSINGHUA UNIV
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