118 results about "Optoelectronic integrated circuits" patented technology

A semiconductor device having at least one layer of a group III-V semiconductor material epitaxially deposited on a group III-V nucleation layer adjacent to a germanium substrate. By introducing electrical contacts on one or more layers of the semiconductor device, various optoelectronic and microelectronic circuits may be formed on the semiconductor device having similar quality to conventional group III-V substrates at a substantial cost savings. Alternatively, an active germanium device layer having electrical contacts may be introduced to a portion of the germanium substrate to form an optoelectronic integrated circuit or a dual optoelectronic and microelectronic device on a germanium substrate depending on whether the electrical contacts are coupled with electrical contacts on the germanium substrate and epitaxial layers, thereby increase the functionality of the semiconductor devices.

An opto-electronic integrated circuit (OEIC) includes an SOI substrate, a set of composite optical transmitters, a set of composite optical receivers, and control electronics disposed in the substrate and electrically coupled to the set of composite optical transmitters and receivers. Each of the composite optical transmitters includes a gain medium including a compound semiconductor material and an optical modulator. Each of the composite optical receivers includes a waveguide disposed in the SOI substrate, an optical detector bonded to the SOI substrate, and a bonding region disposed between the SOI substrate and the optical detector. The bonding region includes a metal-assisted bond at a first portion of the bonding region and a direct semiconductor-semiconductor bond at a second portion of the bonding region. The OEIC also includes control electronics disposed in the SOI substrate and electrically coupled to the set of composite optical transmitters and the set of composite optical receivers.

An optoelectronic integrated circuit for coupling light to or from an optical waveguide formed in an optical device layer in a near-normal angle to that layer. In an embodiment, the integrated circuit comprises a semiconductor body including a metal-dielectric stack, an optical device layer, a buried oxide layer and a semiconductor substrate arranged in series between first and second opposite sides of the semiconductor body. At least one optical waveguide is formed in the optical device layer for guiding light in a defined plane in that device layer. Diffractive coupling elements are disposed in the optical device layer to couple light from the waveguide toward the second surface of the semiconductor body at a near-normal angle to the defined plane in the optical device layer. In an embodiment, an optical fiber is positioned against the semiconductor body for receiving the light from the coupling elements.

A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input / output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input / output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.

A multilayered substrate structure comprising one or more devices, e.g., optoelectronic, integrated circuit. The structure has a handle substrate, which is characterized by a predetermined thickness and a Young's modulus ranging from about 1 Mega Pascal to about 130 Giga Pascal. The structure also has a thickness of substantially crystalline material coupled to the handle substrate. Preferably, the thickness of substantially crystalline material ranges from about 100 microns to about 5 millimeters. The structure has a cleaved surface on the thickness of substantially crystalline material and a surface roughness characterizing the cleaved film of less than 200 Angstroms. At least one or more optoelectronic devices is provided on the thickness of material.

Planar lightwave circuit (PLC) connects optical fibers to the top of an optical or optoelectronic device or optical or optoelectronic integrated circuit. Light propagating through optical fibers is directed to optical waveguides disposed on optical devices. The optical fibers can be in the form of individual fibers, a fiber ribbon or a fiber array. Fiber optic cables can be plugged into a ferrule attached to the PLC. The PLC can also include optical components integrated into the optical path between the optical fibers and the optical device.

A light emitting diode demonstrating high luminescence efficiency and comprising a Group IV semiconductor such as silicon or germanium equivalent thereto as a basic component formed on a silicon substrate by a prior art silicon process, and a fabricating method of waveguide thereof are provided. The light emitting diode of the invention comprises a first electrode for implanting electrons, a second electrode for implanting holes, and a light emitting section electrically connected to the first and the second electrode, wherein the light emitting section is made out of single crystalline silicon and has a first surface and a second surface facing the first surface, wherein with respect to plane orientation (100) of the first and second surfaces, the light emitting section crossing at right angles to the first and second surfaces is made thinner, and wherein a material having a high refractive index is arranged around the thin film section.

An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

A reconfigurable electrical add / drop multiplexing node, a network, and optoelectronic integrated circuit form a novel high capacity fiber-optic integrated transmission and switching system with a baseline target capacity in excess of 1 Tbps. The node, network, and circuit can leverage optoelectronic integration of transmission and switching components along with using the full “transparency” window of modern optical fibers from about 1270 nm to about 1670 nm for a large number of relatively low-rate wavelengths. The electrical switching fabric can be part of a Reconfigurable Electrical Add / Drop Multiplexer (READM) with similar functionality as a Reconfigurable Optical Add / Drop Multiplexer (ROADM) except in a highly integrated fashion with the transmission components. The electrical switching fabric can implement flow switching on a composite signal to provide comparable functionality to optical components in electrical circuitry such as in Complementary metal-oxide-semiconductors.

Provided is an optical transmission substrate including: a first substrate; an optical waveguide which has clad covering a core and a periphery of the core and extends on an upper surface of the first substrate; a second substrate provided parallel to the first substrate so that a lower surface thereof contacts an upper surface of the optical waveguide; a reflection surface which is provided on a cross section of the core at an end of the optical waveguide and reflects light, which travels through the core of the optical waveguide, toward the second substrate; and a light guide which is provided in the second substrate and guides the light, which is reflected toward the second substrate, toward an upper surface of the second substrate from a position closer to the core than an upper surface of the clad.

An optoelectronic integrated circuit is fabricated by forming isolation trenches in a SOI structure to form at least first and second areas of silicon, by forming a first silicon island over the first silicon area during a first silicon forming step such that the first silicon island forms at least a portion of an optical device, by forming a second silicon island over the second silicon area during a second silicon forming step such that the first and second silicon forming steps are separate silicon forming steps, and by processing at least the second silicon area to form an electronic device with the second silicon island.

In the optical connection between multi-layered optical waveguides and photoelectric converting elements or optical waveguide array connectors formed on a substrate, the optical coupling efficiency is to be prevented from degrading due to deviation of the optical axis positions between optical elements and the optical waveguide layers that is caused by a radiation due to a beam expansion or by a deviation of positioning layers in producing the optical waveguides. There are stacked, on a substrate, optical waveguide layers, each of which comprises a clad layer and a core having a higher refractive index than the clad layer, and optical elements formed on the uppermost optical waveguide layer. The optical elements are positioned such that they correspond to the optical path conversion mirrors of the cores of the underlaying optical waveguide layer. The light transmission / reception between the optical elements and the optical path conversion mirrors of the cores of the underlaying optical waveguide layer is performed via the cores of overlying optical waveguide layer.

The invention relates to a germanium-on-insulator (GeOI) structure mixed with patterned single-crystal silicon and a manufacturing method thereof. The GeOI structure is characterized in that an active layer is composed of single-crystal germanium and single-crystal silicon, and the crystal orientation of the single-crystal silicon is determined by substrate silicon. The key point for preparing the structure is to prepare a GeOI single-crystal film. The substrate with the GeOI structure mixed with patterned single-crystal silicon is prepared by the steps of: transferring a single-crystal germanium film on an insulator by using plasma low temperature bonding and low temperature stripping techniques, and performing selective etching and single-crystal silicon epitaxy on the single-crystal germanium film. The inventive GeOI structure mixed with patterned single-crystal silicon can be used for gallium arsenide epitaxy, so as to integrate with III-V semiconductors. Meanwhile, the patterned single-crystal silicon material can be used for conventional CMOS processing to prepare conventional devices and circuits, so as to effectively solve the self healing effect of an embedded oxidation layer. The GeOI structure mixed with patterned single-crystal silicon has important application prospects in high-speed high-performance CMOS devices, optoelectronic integrated circuits, high-speed photodetectors, etc.

The invention provides a photoelectric device based on carbon nano-tube, which uses carbon nano-tube as conductive channel. One end of the photoelectric device has a high work function metal electrode, the other end of the photoelectric device has a low work function metal electrode, the photoelectric device can realize various functional device by simple structure and includes but is not limited to anambipolar field effect transistor, a non-resistance ambipolar diode, a luminescent diode and an optical detector. The invention also provides a large-scale photoelectricity integrated circuit basic unit based on the carbon nano-tube, which uses carbon nano-tube as conductive channel. Two high work function metal electrodes and two low work function metal electrodes are sequentially arranged on the carbon nano-tube, various functional device including electronic device and photoelectric device can be obtained by agilely setting voltage of each electrode. The invention further provides a large-scale photoelectricity integrated circuit capable of realizing various function. In the present invention, function of existing integrated circuit chip is hopeful to greatly increase, novel design thoughts and effective application method can be provided to scale integrated nano circuit.

Power supplies, a ground, and so forth of an analog portion including an image pickup portion 12 are connected to electrode pads 14. Power supplies, a ground, and so forth of a digital portion are connected to electrode pads 15. Thus, various problems such as an increase of impedance of power supplies and a ground, signal crosstalk between each circuit, and noise due to internal line connections between the image pickup portion 12 and a peripheral portion 13 can be prevented.

A polarization splitting grating coupler (PSGC) connects an optical signal from an optical element, such as a fiber, to an optoelectronic integrated circuit. The PSGC separates a received optical signal into two orthogonal polarizations and directs the two polarizations to separate waveguides on an integrated circuit. Each of the two separated polarizations can then be processed, as needed for a particular application, by the integrated circuit. A PSGC can also operate in the reverse direction, and couple two optical signals from an integrated circuit to two respective orthogonal polarizations of one optical output signal sent off chip to an optical fiber.

There is disclosed a method of manufacturing of optical devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and the like. There is further disclosed Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices. According to the present invention there is provided a method of manufacturing an optical device (40), a device body portion (15) from which the device (40) is to be made including a Quantum Well Intermixing (QWI) structure (30), the method including the step of depositing a dielectric layer (51) on at least part of a surface of the device body portion (5) so as to introduce structural defects at least into a portion (53) of the device body portion (5) adjacent the dielectric layer (51). The structural defects substantially comprise "point" defects.

The invention discloses a silicon-based uniwafer photoelectricity integrated receiving chip for plastic optical fiber communication, and relates to a silicon-based uniwafer photoelectricity integrated circuit. The chip is a uniwafer photoelectricity integrated receiving chip with the wavelength of 650 + / - 17.8nm for the plastic optical fiber communication; and a photoelectricity probe chip and a preposed amplifying integrated circuit chip in a light receiving module with the wavelength of 650 + / - 17.8nm for the conventional plastic optical fiber communication can be replaced by the chip, so that the uniwafer photoelectricity integration of the photoelectricity probe and the preposed amplifying integrated circuit with the wavelength of 650 + / - 17.8nm is realized; a requirement on 100Mbps transmission velocity for the plastic optical communication can be met; and the chip can be used for the light receiving end with the wavelength of 650 + / - 17.8nm for the plastic optical fiber communication; and moreover, the chip can be prepared by a 0.5-micron standard binary-coded decimal (BCD).

The invention relates to a method for building a CsPbBr3 nanosheet electroluminescent device by chemical vapor deposition (CVD). The preparation method comprises the steps of loading CsBr powder and PbBr2 powder in a magnetic boat 1 according to a mole ratio being (1.85-2.05):1, laying an ITO glass sheet etched with an electrode on a magnetic boat 2, placing the magnetic boat 1 at a middle part of a horizontal tubular furnace, and placing the magnetic boat 2 at one end, near to an air outlet, of the horizontal tubular furnace; and introducing a carrier gas, discharging air in the furnace, introducing the carrier gas, rising a temperature to a heating temperature being 570-600 DEG C of the magnetic boat 1, rising the temperature to a heating temperature being 300-400 DEG C of the magnetic boat 2, and performing deposition to obtain a product. The CsPbBr3 nanosheet device is built on an ITO electrode initially by a simple method, and light emitting under electric injection is achieved. The obtained device has high-efficiency and stable performance and can be applied to a nanoscale photoelectric integrated circuit.