190 results about "Manycore processor" patented technology

Embodiments of an apparatus and methods for controlling power of a processor having a plurality of cores can independently control individual or selected cores and power supply circuits corresponding to the cores based on, for example, an operation state of the processor or a power mode. Embodiments of an apparatus for controlling power of a processor having a plurality of cores can include a plurality of power supply units each capable of independently supplying a supply power to a plurality of cores provided in one processor, a unit for checking at least one among a use state, a use amount and a power mode of each core and for turning on/off each checked core, and a unit that contacts with the unit for checking for controlling the power supply units in response to an on/off operation of each core.

The invention discloses a multicore processor. The multicore processor comprises a test access port controller and a debugging connector; the test access port controller is provided with an interface connected with a joint test action group (JTAG) simulator; the debugging connector is connected with test access ports of all the cores of the processor; all the test access ports are connected with the debugging connector in parallel; and the test access port controller is used for controlling the debugging connector to connect the cores of the processor to be tested to the simulator. In the processor with the structure, the designs of the standard JTAG port and the test access ports are not needed to be changed. The invention also discloses a system and a method for debugging the multicore processor.

The invention discloses a binding system and method of multiple network interfaces. A Linux operating system and a real-time operating system simultaneously operate based on a multi-core processor. The real-time operating system comprises a physical network interface drive module and a network interface binding processing module aiming at the plurality of network interfaces. The Linux operating system comprises a virtual network interface drive module and a user configuration management interface. The physical network interface drive module is responsible for managing and controlling the network interfaces and receiving and dispatching physical network data. The network interface binding processing module is responsible for obtaining a data package from the physical network interface drive module, processing the received data package according to rules in a data receiving and processing rule base and submitting the processed data package to the virtual network interface drive module at a receiving side. The network interface binding processing module is responsible for receiving data from the virtual network interface drive module, processing the received data package according to a data dispatching rule base and submitting the processed data package to the physical network interface drive module to conduct dispatch at a dispatch side.

The present invention relates to a multicore processor 1. In order to select one of the multiple cores 21, 22, 23 in such a processor, an execution time of tasks which are performed multiple times is determined Based on the determined execution time on the individual cores 21, 22, 23, an appropriate core 21, 22, 23 for further executions of a task is selected. Additionally, the present invention further provides a code generator and code generating method for providing appropriate machine code for a multicore processor 1.

An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing.

The present invention provides debugging in a multi-core architecture. A method of monitoring thread execution within a multi-core processor architecture comprising a plurality of interconnected processor units for processing threads, the method comprising: receiving a plurality of thread parameter indicators, the thread The parameter indicator represents one or more parameters related to the function and/or identity and/or execution location of one or more threads; comparing at least one of these thread parameter indicators with a first plurality of predetermined criteria, Each of the first plurality of predetermined criteria represents an indicator of interest; and generating an output based on thread parameter indicators identified as being of interest as a result of said comparing.

A test method for a master-slave concurrent system running on a multicore processor includes the steps of establishing a PFA, otherwise called probabilistic finite automata, or probabilistic finite state machine, for a given regular expression; generating test patterns by running the PFA; splitting and merging the test patterns to generate an interleaved test pattern; and performing test on the master-slave system according to the interleaved test pattern. In an embodiment, the method further includes a step of debugging failures of the multicore processor during testing.

Different cores of a multicore processor are used to provide diagnostics of sophisticated hardware without full redundancy by static assignment of the cores during individual cycles of the control program and comparison of the outputs. A method of automatically generating diverse programs for execution by these cores may modify one program to compile two different instructions without functionally changing that program through the use of DeMorgan equivalents and diverse compiler optimizations.

The invention provides a multicore processor-oriented internal memory management system. The system is characterized by dividing progress memory access behaviors into a static attribute and a dynamic attribute, wherein the static attribute is used for describing general internal memory demand behaviors (sing-page or burst-mode requests) represented by progresses; the dynamic attribute is used for describing the characteristics represented by the progresses for internal memory requirements in the life cycle active processes of the progresses; and on the basis of analysis carried out on the static attribute and the dynamic attribute, internal memory operation modules in and between the progresses are imported. The system can be used for effectively improving the system distribution efficiency and effectively reducing the competition of internal memory resource locks between multiple cores.

The invention relates to a method for executing computer usable program code or a program made up of program parts on a multi-core processor (1) with a multiplicity of execution units (21, 22, 23, 24), each of which comprises a local memory (201) and at least one processing unit (202) communicatively linked to the local memory, wherein each of the execution units (21, 22, 23, 24) is connected to a communications network (30) for data exchange. One or more program parts are stored in at least some of the local memories (201) of the majority of execution units (21, 22, 23, 24). Execution of a program part is performed by the processing unit (202) of the particular execution unit (21, 22, 23, 24) that has the program part stored in its local memory (201).