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165 results about "Electron trapping" patented technology

Light-Emitting Device and Electronic Device

The present invention provides light-emitting devices having excellent characteristics and electronic devices having excellent characteristics, having such light-emitting devices. Specifically, the present invention provides a light-emitting device includes a first light-emitting element, a second light-emitting element, and a third light-emitting element which emit light having different color from each other. The first light-emitting element includes a first anode; a first cathode; and a first light-emitting layer and a second light-emitting layer between the first anode and the first cathode, wherein the first light-emitting layer includes a first high light-emitting substance and a first organic compound, and the second light-emitting layer includes the first high light-emitting substance and a second organic compound, wherein the first light-emitting layer is in contact with the first anode side of the second light-emitting layer, and wherein the first organic compound is an organic compound having a hole-transporting property and the second organic compound is an organic compound having an electron-transporting property. The second light-emitting element includes a second anode; a second cathode; and a third light-emitting layer and a layer for controlling carrier transfer between the second anode and the second cathode, wherein the third light-emitting layer includes a second high light-transmitting substance, wherein the layer for controlling carrier transfer includes a third organic compound and a fourth organic compound, and is provided between the third light-emitting layer and the second cathode, wherein the third organic compound is an organic compound having an electron-transporting property and the fourth organic compound is an organic compound having an electron-trapping property; and wherein the third organic compound is included more than the fourth organic compound in the layer for controlling carrier transfer. The third light-emitting element includes a third anode; a third cathode; and a fourth light-emitting layer, wherein the fourth light-emitting layer includes a fifth organic compound, a sixth organic compound, and a third high light-emitting substance, wherein the fifth organic compound is an organic compound having a hole-transporting property, and the sixth organic compound is an organic compound having an electron-transporting property, and wherein the third high light-emitting substance is a substance which emits phosphorescence.
Owner:SEMICON ENERGY LAB CO LTD

Complementary metal-oxide semiconductor (CMOS) devices including a thin-body channel and dual gate dielectric layers and methods of manufacturing the same

A complementary metal-oxide semiconductor (CMOS) device includes an NMOS thin body channel including a silicon epitaxial layer. An NMOS insulating layer is formed on a surface of the NMOS thin body channel and surrounds the NMOS thin body channel. An NMOS metal gate is formed on the NMOS insulating layer. The CMOS device further includes a p-channel metal-oxide semiconductor (PMOS) transistor including a PMOS thin body channel including a silicon epitaxial layer. A PMOS insulating layer is formed on a surface of and surrounds the PMOS thin body channel. A PMOS metal gate is formed on the PMOS insulating layer. The NMOS insulating layer includes a silicon oxide layer and the PMOS insulating layer includes an electron-trapping layer, the NMOS insulating layer includes a hole trapping dielectric layer and the PMOS insulating layer includes a silicon oxide layer, or the NMOS insulating layer includes a hole-trapping dielectric layer and the PMOS insulating layer includes an electron-trapping dielectric layer.
Owner:SAMSUNG ELECTRONICS CO LTD

Method for fabricating non-volatile memory

A method of fabricating a non-volatile memory is described. A substrate is provided and a first dielectric layer, an electron trapping layer and a second dielectric layer are sequentially formed thereon. Each of the stacked gate structures includes a first gate and a cap layer having a gap between every two stacked gate structures. An oxide layer is formed on the sidewalls of the first gate. A portion of the second dielectric layer not covered by the stacked gate structures is removed. A third dielectric layer is further formed on the substrate. A second conductive layer is formed over the substrate, and a portion thereof to form second gates. The second gates and the stacked gate structures form a column of memory cells. A source region and a drain region are formed in the substrate adjacent to two sides of the column of memory cells.
Owner:POWERCHIP SEMICON MFG CORP

Method for manufacturing device isolation film of semiconductor device

ActiveUS20060024912A1Improving semiconductor device characteristicHEIP phenomenon is reduced or preventedSemiconductor/solid-state device manufacturingSemiconductor devicesDevice materialTrapping
A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.
Owner:SK HYNIX INC
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