42results about How to "Reduce rise and fall times" patented technology

A driving unit for a liquid crystal display device is provided. The driving unit includes a first group of driving stages and a second group of driving stages. A first driving stage of the first group receives a first gate start voltage. The first group of driving stages sequentially outputs scan signals according to a first clock signal. The scan signal outputted by one driving stage of the first group is sent to a next subsequent driving stage of the first group. A first driving stage of the second group receives a second start voltage. The second group of driving stages sequentially outputs the scan signals according to a second clock signal. The scan signal outputted by one driving stage of the second group is sent to a next subsequent driving stage of the second group. The driving stages of the first group and the second group alternately output the scan signals.

It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

A method of driving an IPS mode LCD includes applying a common voltage to a common electrode of the LCD panel, the LCD panel including a liquid crystal (LC) cell and driving the LC cell to express light at a predetermined brightness level associated with a predetermined data signal voltage applied to a pixel electrode, the driving including applying a compensation voltage to the LC cell prior to applying the predetermined data signal voltage, wherein a voltage difference between a previously applied data signal voltage and the compensation voltage is greater than a voltage difference between a previously applied data signal voltage and the predetermined data signal voltage.

A boost circuit is arranged to reduce rise and fall times of pulsed power used for pulsed control operation of electric machines. Magnetic energy present in the electric machine at the end of a pulse is extracted by the boost circuit to reduce the pulse fall time. The energy is stored by the boost circuit and then applied at the beginning of a subsequent pulse to reduce the rise time. By reducing rise and fall times compared to not using such a boost circuit, machine efficiency is improved.

The invention discloses a gate driving circuit unit and a gate driving circuit. The gate driving circuit unit comprises a driving control module, a driving module, a low-level maintaining module, a scanning signal output end and a transmission signal output end. The driving control module further comprises bootstrap series units. The gate driving circuit comprises the gate driving circuit units in N-grade cascade connection. The driving control module of the gate driving circuit unit controls the driving module to be in a charging or discharging state according to an input signal; the driving module charges the scanning signal output end and the transmission signal output end in a charging state and discharges the scanning signal output end and the transmission signal output end in a discharging state. According to the design of bootstrap series units, when the threshold voltage of a transistor is negative, electric leakage at a driving control end can be inhibited; when the threshold voltage of the transistor is positive, charging of the driving control end can be accelerated, so that rising/dropping time of an output signal is shortened, and the threshold voltage application range of the circuit is expanded.

A frequency converter (100) is provided, comprising: a pulse generator (150) configured to receive a balanced local oscillator signal pair and to generate a balanced rectangular pulse signal pair having the reference frequency; and a mixer (160) configured to mix an input signal having an input frequency with the balanced rectangular pulse signal pair to generate an output signal having an output frequency. The input frequency is different from the output frequency, and the pulse generator and the mixer are formed on a single integrated circuit (120). The frequency converter may comprise a balanced local oscillator (110) configured to generate the balanced local oscillator signal pair. The balanced local oscillator may comprise: an unbalanced local oscillator (130) configured to provide an unbalanced local oscillator signal having the reference frequency; and a balun (140) configured to generate the balanced local oscillator signal pair based on the unbalanced local oscillator signal.

Disclosed herein is a CML circuit that can solve a conventional problem that it has been impossible to input a large amplitude signal to a differential pair. The CML circuit of the present invention includes an internal signal generation circuit for generating an input differential signal having an amplitude to be ranged approximately from a ground potential to a power supply potential, a first MOS transistor having a gate for inputting a differential signal having one of the two amplitudes, a second MOS transistor having a gate for inputting a differential signal having the other of the two amplitudes and having a common source shared with the first MOS transistor, a first resistance element connected between the drain of the first MOS transistor and a first power supply terminal, a second resistance element connected between the drain of the second MOS transistor and the first power supply terminal, a third MOS transistor connected to the first resistance element in parallel, and a fourth MOS transistor connected to the second resistance element in parallel.

The invention discloses a bootstrap sampling switch circuit, a sampling hold circuit and an analog-to-digital converter. The bootstrap switching circuit comprises: a voltage regulator used for generating a first voltage and a second voltage, wherein the first voltage is equal to the sum of a common-mode voltage and a third voltage, and the second voltage is equal to the sum of the common-mode voltage and the third voltage; a level shift circuit, wherein the level shift circuit takes a first voltage as a power supply voltage and is used for generating a clock, the high level of the clock is equal to the first voltage, and the low level of the clock is equal to the second voltage; and a bootstrap main circuit, wherein the bootstrap main circuit takes a first voltage as a power supply voltageand takes a second voltage as ground, and the bootstrap main circuit is controlled by the clock and is used for generating a constant voltage at a gate-source end of the switching tube. The MOS tubesin the circuit are low-voltage thin gate tubes. The bootstrap sampling switching circuit is realized by adopting the low-voltage thin gate tube, so that the ascending and descending time of an outputclock is greatly shortened on the premise of not sacrificing the swing amplitude of an input signal, and the ADC sampling rate is greatly improved.

The present invention discloses a method for improving the timing margin of a NandFlash bus. The method comprises the following steps: calculating a load capacitance value according to a storage capacity; determining a target capacitance value according to a signal rise time requirement; and serially connecting a series capacitor to the DQ and DQS signals, and determining a capacitance value of aseries capacitor according to the load capacitance value and the target capacitance value. According to the method for improving the timing margin of a NandFlash bus disclosed by the present invention, by using the principle that after two capacitors are connected in series, the equivalent capacitance is smaller than the capacitance of any one of the series capacitors, and by serially connecting the series capacitors in the IO signal link, the timing margin of the bus is improved, the contradiction between the large capacity and the high speed is solved, and consideration of both of the largecapacity and the high speed can be achieved.

The present invention relates to a dental radiography device capable of: reducing the amount of radiation exposure and the amount of battery consumption by reducing radiation exposure time by using a high switching frequency of 100 kHz or greater; preventing occurrence of operation errors caused by a momentary high voltage, etc. while using the high switching frequency; and easily setting X-ray irradiation time according to the type of teeth. Thus, the dental radiography device is safe, accurate and easy to use, and can have a small size and light weight.

With a large capacity of an optical disk and high-speed recording, a frequency of a recording signal is increased and a pulse width is narrowed. In the case that a laser is driven by a signal having the short pulse width, unfortunately the high-speed recording is hardly performed to an optical disk when a rise time and a fall time of the optical pulse are lengthened.

During user data recording, a bottom driving current is set to a second bottom driving current value that is a current value of a threshold or less, so that the rise time and the fall time of the optical pulse can be shortened to perform the high-speed recording of the optical disk.

The invention provides a voltage level switching circuit. The voltage level switching circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. The sixth transistor and the seventh transistor are arranged to provide equivalent high resistance, and the latch capacity of the third transistor and the fourth transistor is reduced. When the voltage difference of the input voltage is in a low level, the state of the circuit can be switched smoothly. The fifth transistor and the eighth transistor are arranged to provide a breakover path, the rising time or the falling time of output signals can be shortened. Under the demand of the same switching time, compared with the prior art, the voltage level switching circuit is advantaged in that the layout area and dynamic current consumption can be reduced.