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45results about How to "Reduce effective width" patented technology

Inner truss type steel tube concrete L-shaped column and construction method thereof

The invention discloses an inner truss type steel tube concrete L-shaped column and a construction method thereof. The inner truss type steel tube concrete L-shaped column comprises a wrapping steel tube, filling concrete and an inner truss; the inner truss comprises T-shaped steel, inner truss subunits and T-shaped steel web lacing bars; the inner truss subunits are formed by welding the T-shaped steel; the T-shaped steel web lacing bars are longitudinally welded in a T-shaped steel web and the inner truss subunits along the T-shaped steel in a stacked manner; the T-shaped steel and the inner truss subunits are positioned at edges and corners of a quadrangle; the cross section of the wrapping steel tube is inversely L-shaped or n-shaped; and the wrapping steel tube is fixedly welded with flange plates of the T-shaped steel. The inner truss is tensioned at a corner of a special-shaped steel tube, so that effective width of a steel plate is reduced, a fulcrum is provided for deformation of the steel plate out of a plane, anti-unsteady capability of the steel plate can be improved, a hooping effect of the column is improved, and the bearing capacity of a steel tube concrete special-shaped column is improved obviously.
Owner:HOHAI UNIV

Super junction semiconductor device manufacturing method capable of improving avalanche capacity

The invention relates to a super junction semiconductor device manufacturing method capable of improving the avalanche capacity. On-resistance is increased correspondingly due to transverse diffusion caused by the traditional high dosage concentration of a column P, and puncture voltage is reduced due to electric charge unbalance of the column P and a column N. According to the method, the epitaxy technology is utilized to form an N-type epitaxy layer; a P-type and N-type epitaxy layer is formed by injecting boron ions; the injection amount of the boron ions increases gradually, and the boron ions are pushed under the high temperature to form a P-type and N-type alternant epitaxy layer; a Pbody area is formed by injecting the boron ions; a polycrystalline silicon gate electrode is formed by etching polycrystalline silicon through the dry method; an N+ source area is formed by injecting arsenic ions; a layer of aluminum is deposited on the upper surface of a whole device, a source metal electrode is formed by etching the aluminum, and a drain electrode is formed on the back face through metallization. According to the super junction semiconductor device obtained through the method, the avalanche capacity of the super junction semiconductor device is improved, and at the same time, on-resistance is reduced.
Owner:XIAN LONTEN RENEWABLE ENERGY TECH +1

Support structure apparatus and method

A support structure for supporting and tilting an oversized cargo to reduce the effective width of the cargo. The structure comprises a frame having a base and a stanchion connected to the base. A rocker arm is pivotally coupled to the stanchion to pivot about a pivot axis. The arm includes a first and second end disposed opposite one another. The arm has a center of gravity disposed between the first end and the pivot axis and that biases the arm to pivot in a first pivotal direction. First and second brackets are positioned near the first and second ends of the arm for receiving the cargo. The cargo has a center of gravity disposed between the pivot axis and the second end that causes the arm to pivot in a second pivotal direction opposite the first pivotal direction.
Owner:CRETEX

A mos device for integrated circuit chip esd protection

InactiveCN103280458BImprove turn-on uniformityIncrease the secondary breakdown currentSemiconductor devicesElectrical resistance and conductancePower flow
The invention relates to an MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of an integrated circuit chip, belonging to the technical field of electronics. On the premise that the size of the device is not increased and more chip area is not required to be consumed, substrate resistance between a source region and a substrate contact region is increased by adding a plurality of strip-shaped well regions which are in parallel with the transverse direction of the device in a substrate region below a position between the source region and the substrate contact region, so that the ESD resisting ability of the device is improved; besides, the size of the substrate resistance of the device can be adjusted and the problem of poor starting uniformity of the device can be solved by adjusting the quantity and the width of the strip-shaped well regions and the mutual distances among the strip-shaped well regions, so that the secondary breakdown current of the device is further improved; meanwhile, the manufacturing process of the MOS device is compatible with the standard CMOS process. In conclusion, the MOS device for the ESD protection of the integrated circuit chip provided by the invention has stronger ESD resisting ability due to the increase of the substrate resistance and the production cost of the device is not increased because the size of the device is not increased.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA +1

Area-Efficient Single-legged SOI MOSFET structure immune to single-event-effects and bipolar latch-up

New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionization current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body / Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) implant into the device structure that increases the total device periphery without correspondingly scaling its device current.
Owner:TARAKJI AHMAD HOUSSAM

Apparatus and method for the concurrent converting of multiple web materials

An apparatus for the concurrent converting of multiple web products includes at least a first unwind station and a second unwind station. The apparatus further includes a first web transformation station associated with a first web material unwound from the first unwind station, and a second web transformation station associated with the second web material unwound from the second unwind station. The first and second web transformation stations are disposed such that less than twice the width of the widest web material separates a portion of the first web material in the first web transformation station from a portion of the second web material in the second web transformation station. The method of the invention includes steps of unwinding web materials from rolls at each of the first and second unwind stations and transforming the respective web materials using the first and second web transformation stations.
Owner:THE PROCTER & GAMBNE CO

Current sampling circuit achieved through LDMOS devices

The invention discloses a current sampling circuit achieved through LDMOS devices. A sampling tube and a sampled tube are both the LDMOS devices, the sampling tube is arranged in the middle area of the sampled tube, and the effective width of a source region of the sampling tube is determined by the contact width of an N+ region of the resource region and a grid electrode. A voltage resisting buffer layer is arranged in a drift region of a drain region of the sampling tube, the voltage resisting buffer layer can define the effective drain region drift region aligned to the effective part of the source region, and meanwhile the surrounding range of the whole drain region drift region is not reduced. The sampling ratio of the circuit can be improved by reducing the effective width of the source region, and due to the fact that the effective drain region drift region is aligned to the N+ region of the source region, parasitic resistance between the source region and the drain region of the sampling tube and parasitic resistance between the source region and the drain region of the sampled tube are in proportion, and the stability of the sampling ratio can be improved. The matching degree and stability of the sampling tube and the sampled tube can be improved, the occupied area of the circuit can be reduced, and the integration degree can be improved.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of integrated circuit chip

InactiveCN103280458AImprove turn-on uniformityIncrease the secondary breakdown currentSemiconductor devicesElectrical resistance and conductanceEngineering
The invention relates to an MOS (Metal Oxide Semiconductor) device for ESD (Electrostatic Discharge) protection of an integrated circuit chip, belonging to the technical field of electronics. On the premise that the size of the device is not increased and more chip area is not required to be consumed, substrate resistance between a source region and a substrate contact region is increased by adding a plurality of strip-shaped well regions which are in parallel with the transverse direction of the device in a substrate region below a position between the source region and the substrate contact region, so that the ESD resisting ability of the device is improved; besides, the size of the substrate resistance of the device can be adjusted and the problem of poor starting uniformity of the device can be solved by adjusting the quantity and the width of the strip-shaped well regions and the mutual distances among the strip-shaped well regions, so that the secondary breakdown current of the device is further improved; meanwhile, the manufacturing process of the MOS device is compatible with the standard CMOS process. In conclusion, the MOS device for the ESD protection of the integrated circuit chip provided by the invention has stronger ESD resisting ability due to the increase of the substrate resistance and the production cost of the device is not increased because the size of the device is not increased.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA +1

Support structure apparatus and method

A support structure for supporting and tilting an oversized cargo to reduce the effective width of the cargo. The structure comprises a bolster frame having a base and a stanchion connected to the base. The stanchion extends upwardly from a lower end connected to the base to an upper end opposite the lower end. A cylindrical roller supported is by the upper end of the stanchion for rotational movement relative to the stanchion about a rotational axis. The cylindrical roller is also supported by the stanchion for pivotal movement relative to the stanchion such that the rotational axis pivots relative to the stanchion. The bolster frame also includes a bearing pad connected to the base. The cylindrical roller and the bearing pad at least partially support the oversized cargo. The support structure may be mounted on a trailer for transporting oversized cargo, such as concrete double-tees.
Owner:CRETEX

High-threshold power semiconductor device and manufacturing method thereof

ActiveCN112164725AReduce the effective channel widthGood uniformity over a large areaSemiconductor/solid-state device manufacturingSemiconductor devicesCapacitancePower semiconductor device
The invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device sequentially comprises a drain metal electrode, asubstrate, a buffer layer and a drift region from bottom to top, and also comprises: a composite column body on the drift region, formed by a drift region protrusion, a columnar p region and a columnar n region, and a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a gate metal electrode and a source metal electrode. The composite column body is formedby sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching the p-type semiconductor layer and the n-type semiconductor layer; wherein the channel layer and the passivation layer are formed by deposition in sequence. Therefore, the device is divided into a cellular region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the gate metal electrode and the source metal electrode only exist in the cellular region, and the passivation layer of the terminal region extends upwards and wraps the outerside of the channel layer. The structure can improve the threshold voltage of the device, improve the blocking characteristic of the device, and reduce the gate capacitance.
Owner:SOUTHEAST UNIV

A polymer lithium ion battery and a preparation method thereof

The invention discloses a polymer lithium ion battery, characterized by comprising a battery body (5), the exterior of the battery body (5) is provided with a battery case (50), and left and right sides of the battery case (50) are respectively provided with a stepped side (2). In addition, the invention also discloses a preparation method of a polymer lithium ion battery. The invention disclosesa polymer lithium ion battery and a preparation method thereof, which can effectively encapsulate polymer lithium ion batteries, the side edge of the polymer lithium ion battery is ultra-thin, and theeffective width of the battery can be reduced; the technical scheme provides more space and possibility for the capacity improvement of the battery, and ensures the good sealing property of the polymer lithium ion battery, effectively avoids the bad resistance of the shell and the corrosion of the electrolyte to the aluminum plastic shell; the battery can be conveniently manufactured, which is beneficial to the wide application and has great significance in the production practice.
Owner:TIANJIN LISHEN BATTERY
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