Current sampling circuit achieved through LDMOS devices

Abstract

The invention discloses a current sampling circuit achieved through LDMOS devices. A sampling tube and a sampled tube are both the LDMOS devices, the sampling tube is arranged in the middle area of the sampled tube, and the effective width of a source region of the sampling tube is determined by the contact width of an N+ region of the resource region and a grid electrode. A voltage resisting buffer layer is arranged in a drift region of a drain region of the sampling tube, the voltage resisting buffer layer can define the effective drain region drift region aligned to the effective part of the source region, and meanwhile the surrounding range of the whole drain region drift region is not reduced. The sampling ratio of the circuit can be improved by reducing the effective width of the source region, and due to the fact that the effective drain region drift region is aligned to the N+ region of the source region, parasitic resistance between the source region and the drain region of the sampling tube and parasitic resistance between the source region and the drain region of the sampled tube are in proportion, and the stability of the sampling ratio can be improved. The matching degree and stability of the sampling tube and the sampled tube can be improved, the occupied area of the circuit can be reduced, and the integration degree can be improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a current sampling circuit realized by LDMOS devices. Background technique [0002] The LDMOS device is a high withstand voltage field effect transistor, which can be used to form a current sampling circuit. Such as figure 1 Shown is a schematic diagram of an existing current sampling circuit implemented with an LDMOS device. The existing current sampling circuit implemented with LDMOS devices includes an LDMOS device 1 for current sampling and an LDMOS device 2 for current comparison, and the gate 3 and drain 4 of the LDMOS device 1 for current sampling and the LDMOS device 2 for current comparison are connected in common, The source 5A and 5B are connected separately [0003] Such as figure 2 As shown in FIG. 2 , it is a schematic diagram of the layout structure of the first current sampling circuit realized by LDMOS devices. The area indicated by the dotted line box ...

AI Technical Summary

Problems solved by technology

But the disadvantages of this design are: 1. The sampling tube and the sampled tube are placed in two places. Although they are very close to each other, due to the large current of the sampled tube, they will generate heat during work, and the heat will cause the current capacity to drop. The current capacity of the sampling tube is small, the heat generated during work is very small, and the current capacity is almost unaffected

[0014] but also as image 3 The structure shown also has its disadvantages: the effective width of the source region 309 is relatively large, and the sampling current of the sampling tube will also be relatively large, which will reduce the sampling ratio of the circuit. The length of the major axis of the racetrack structure increases the sampling ratio of the circuit, but the reduction of the length of the major axis of the racetrack structure reduces the withstand voltage capability of the device; so the existing device structure cannot simultaneously improve the sampling ratio and withstand voltage capability of the device

like Figure 5C The relationship between the sampling ratio and the drain voltage shown in the graph shows that although the design of the sampling tube and the size of the sampled tube are exactly the same, the sampling ratio is 100+ / - in the range of the drain voltage from 0 volts to 10 volts. 20, the deviation is + / -20%, but its sampling ratio is only 100, which is very small

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