42results about How to "Reduce calculation delay" patented technology

The present invention relates to a user-authenticable outsourced image denoising method based on privacy protection, comprising the steps of: a trusted third party TTP to the content owner CO, authorized user AU and two edge computing servers ES 1 、ES 2 Assign relevant keys; CO first encrypts the noisy image with the key assigned by TTP, and sends the encrypted image to the first edge computing server ES 1 ; The second edge computing server ES 2 Auxiliary first edge computing server ES 1 Perform ciphertext image denoising, and send the calculated results to the first edge computing server ES 1 ; AU makes an image usage request to the corresponding CO, and the first edge computing server ES 1 Obtain the corresponding denoised ciphertext image, and with the help of its own private key, the authorized user AU decrypts and restores the required plaintext denoised image. The invention ensures the security of user privacy data and provides image denoising service at the same time; and reduces the user's local computing and communication expenses, and its ciphertext denoising effect is almost equal to the plaintext domain performance.

The invention discloses an FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication. The circuit comprises a real part calculation module and an imaginary part calculation module, wherein the real part calculation module is used for calculating a real part in complex multiplication and calculating real parts of X and Y in butterfly operation, and the imaginary part calculation module is used for calculating an imaginary part in complex multiplication and calculating imaginary parts of X and Y in butterfly operation. The circuit has the advantages of capabilities of reducing hardware cost, decreasing calculation delay and improving calculation accuracy and the like.

The invention provides a method, a device and a system for modulating a zero sequence voltage pulse width of a three-phase four-legged APF (active power filter). The method comprises the following steps of solving a zero sequence component according to a reference value of a voltage of midpoints of legs A, B and C of the three-phase four-legged arm APF to a midpoint of a leg N of the three-phase four-legged arm APF; controlling a pulse duty ratio according to a reference value of a voltage of a calculating point N of the three-phase four-legged APF to a point O of a cathode of a direct-current bus capacitor and a switch tube of the leg N; and solving a voltage of the midpoints of the legs A, B and C of the three-phase four-legged APF to the point O of the cathode of the direct-current bus capacitor and a corresponding duty ratio. A zero sequence voltage linear control pulse width modulation strategy is applied to the three-phase four-legged APF. Compared with the traditional 3D-SVPWM (three-dimensional space vector pulse width modulation) strategy, the zero sequence voltage linear control pulse width modulation strategy is easy to implement and can reduce calculation delay and requirements on main frequency; and the response speed of the three-phase four-legged APF can be increased further, the harmonic compensation accuracy of the three-phase four-legged APF can be improved, hardware investment is saved, and the method has an important practical significance on practical degree of a project of the three-phase four-legged APF.