42results about How to "Reduce calculation delay" patented technology

The present invention relates to a user-authenticable outsourced image denoising method based on privacy protection, comprising the steps of: a trusted third party TTP to the content owner CO, authorized user AU and two edge computing servers ES 1 、ES 2 Assign relevant keys; CO first encrypts the noisy image with the key assigned by TTP, and sends the encrypted image to the first edge computing server ES 1 ; The second edge computing server ES 2 Auxiliary first edge computing server ES 1 Perform ciphertext image denoising, and send the calculated results to the first edge computing server ES 1 ; AU makes an image usage request to the corresponding CO, and the first edge computing server ES 1 Obtain the corresponding denoised ciphertext image, and with the help of its own private key, the authorized user AU decrypts and restores the required plaintext denoised image. The invention ensures the security of user privacy data and provides image denoising service at the same time; and reduces the user's local computing and communication expenses, and its ciphertext denoising effect is almost equal to the plaintext domain performance.

An embodiment of the present invention provides a stacking network processor and a network data stacking processing method. The network processor includes: a storage module, including a header memory and a payload memory, for storing protocol headers and data payloads respectively; a framing module, It is used to obtain the corresponding protocol header and data load from the storage module according to the operation instruction, and after replacing or inserting the preset part of the obtained protocol header, output the data frame to be verified; the verification module is used to verify the After the data frame to be verified is verified, a verification result is obtained; the framing module is further configured to obtain a final data frame according to the data frame to be verified and the verification result, and output it to the network. The network processor does not need to store the entire final data frame before sending it, which can reduce the delay caused by storage. In addition, it is implemented through network hardware modules, which can effectively reduce the calculation delay.

The invention belongs to the technical field of high-performance public key cryptographic integrated circuits and particularly relates to an extensible modular multiplier circuit based on an improved Montgomery modular multiplication algorithm. According to the extensible modular multiplier circuit based on the improved Montgomery modular multiplication algorithm, by introducing an extra parameter, the data bit width of a Montgomery field can be reduced, and further the hardware cost of a whole system can be reduced. The invention also designs a high-performance extensible multiplier circuit based on the improved Montgomery modular multiplication algorithm. The high-performance extensible multiplier circuit is mainly composed of a time schedule controller, a partial product generating circuit, a carry storage summator compressed tree circuit, a partial product feedback circuit, a modular multiplier extension correlated circuit and a time schedule controller. The high-performance extensible multiplier circuit achieves modular multiplication with a relatively large bit width through cooperation of a plurality of modular multipliers, thereby reducing computation time delay, achieving good extending performance and obviously improving the modular multiplication efficiency.

The invention discloses an FFT (fast Fourier transform) butterfly operation hardware implementation circuit supporting complex multiplication. The circuit comprises a real part calculation module and an imaginary part calculation module, wherein the real part calculation module is used for calculating a real part in complex multiplication and calculating real parts of X and Y in butterfly operation, and the imaginary part calculation module is used for calculating an imaginary part in complex multiplication and calculating imaginary parts of X and Y in butterfly operation. The circuit has the advantages of capabilities of reducing hardware cost, decreasing calculation delay and improving calculation accuracy and the like.

The disclosure provides an underwater sensor and a positioning system. Wherein, an underwater sensor includes a ReRAM and a controller, and the controller is connected to the ReRAM; the ReRAM includes a memory module and a Euclid measurement module; the memory module is used for buffering input data; the Euclid The Reed measurement module includes several parallel measurement modules, each parallel measurement module includes an addition calculation module, a square root calculation module and several parallel calculation modules; the parallel calculation module includes a first subtraction array and a first multiplication array; The parallel calculation module is used for parallel calculation of each addend in the Euclidean metric formula; the addition calculation module is used to complete the summation process of the operation results of each unit of the parallel calculation module, and use the result as the square root calculation Input data for the module.

The invention provides a method, a device and a system for modulating a zero sequence voltage pulse width of a three-phase four-legged APF (active power filter). The method comprises the following steps of solving a zero sequence component according to a reference value of a voltage of midpoints of legs A, B and C of the three-phase four-legged arm APF to a midpoint of a leg N of the three-phase four-legged arm APF; controlling a pulse duty ratio according to a reference value of a voltage of a calculating point N of the three-phase four-legged APF to a point O of a cathode of a direct-current bus capacitor and a switch tube of the leg N; and solving a voltage of the midpoints of the legs A, B and C of the three-phase four-legged APF to the point O of the cathode of the direct-current bus capacitor and a corresponding duty ratio. A zero sequence voltage linear control pulse width modulation strategy is applied to the three-phase four-legged APF. Compared with the traditional 3D-SVPWM (three-dimensional space vector pulse width modulation) strategy, the zero sequence voltage linear control pulse width modulation strategy is easy to implement and can reduce calculation delay and requirements on main frequency; and the response speed of the three-phase four-legged APF can be increased further, the harmonic compensation accuracy of the three-phase four-legged APF can be improved, hardware investment is saved, and the method has an important practical significance on practical degree of a project of the three-phase four-legged APF.