35results about How to "Prevent charge leakage" patented technology

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

This invention provides redox-active molecules attached to polypodal (e.g., bipodal, tripodal, quadrapodal, pentapodal, etc.) tethers that can be used for attachment of the redox-active molecules to a substrate (e.g., an electrode). The tethered redox-active molecules are useful for the fabrication of memory devices.

A pixel image sensor has a high shutter rejection ratio that prevents substrate charge leakage to a floating diffusion storage node of the pixel image sensor and prevents generation of photoelectrons within the floating diffusion storage node and storage node control transistor switches of the pixel image sensor. The pixel image sensor that prevents substrate charge leakage of photoelectrons from pixel image sensor adjacent to the pixel image sensor. The pixel image sensor is fabricated on a substrate with an isolation barrier and a carrier conduction well. The isolation barrier formed underneath the floating diffusion storage node allows effective isolation by draining away the stray carriers and preventing them from reaching the floating diffusion storage node. The carrier conduction well in combination with the deep N-well isolation barrier separates the pinned photodiode region from the deep N-well isolation barrier that is underneath the floating diffusion storage node.

This invention provides novel high density memory devices (FIG. 3) that are electrically addressable permitting effective reading and writing, that provide a high memory density (102), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices arc intrinsically latchable, defect tolerant, and support destructive or non-destructive read cycles. In a preferred embodiment, the device comprises a fixed electrode electrically coupled to a storage medium having a multiplicity of different and distinguishable oxidation states wherein data is stored in said oxidation states by the addition or withdrawal of one or more electrons from said storage medium via the electrically coupled electrode.

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

This invention provides a new method of forming a self-assembling monolayer (SAM) of alcohol-terminated or thiol-terminated organic molecules (e.g. ferrocenes, porphyrins, etc.) on a silicon or other group IV element surface. The assembly is based on the formation of an E-O— or an E-S— bond where E is the group IV element (e.g. Si, Ge, etc.). The procedure has been successfully used on both P- and n-type group IV element surfaces. The assemblies are stable under ambient conditions and can be exposed to repeated electrochemical cycling.

Provided are a non-volatile memory device and a method of manufacturing the non-volatile memory device. The non-volatile memory device includes a charge trap layer having a crystalline material. In the method, a tunneling insulating layer is formed on a substrate, and a crystalline charge trap layer is formed on the tunneling insulating layer.