48results about How to "Minimize data transfer" patented technology

Systems and methods are disclosed that facilitate minimizing data transfer from a post office protocol (POP) server to a client device by employing a date filter with a predefined date range and applying a message body size threshold above which only a message header will be downloaded to conserve bandwidth and/or memory space on the client device. A user can request download of a message for which only a message header was originally downloaded if the header comprises information of interest to the user.

The present invention finds candidate objects for remote differential compression. Objects are updated between two or more computing devices using remote differential compression (RDC) techniques such that required data transfers are minimized. An algorithm provides enhanced efficiencies for allowing the receiver to locate a set of objects that are similar to the object that needs to be transferred from the sender. Once this set of similar objects has been found, the receiver may reuse any chunks from these objects during the RDC algorithm.

A multi-chip touch architecture for scalability can include one or more touch controller application specific integrated circuits (ASICs), and one or more switching circuits coupled between the one or more touch controller ASICs and the touch sensor panel. The number of touch controller ASICs and switching circuits can be scaled based on the size of the touch sensor panel. The touch controller ASICs can include an interface for data transfer between the touch controller ASICs to allow for parallel processing of an image of touch by more than one touch controller ASIC. The touch controller ASIC can also include a memory directly accessible by more than one processing circuit (e.g., hardware accelerators), and circuitry to dynamically adjust the coupling between portions (e.g., banks) of memory and inputs of the one or more processing circuits to minimize data transfer and improve processing speeds.

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe and also a write data strobe that is out-of-phase relative to the read data strobe, and presents data synchronously with one of the edges of that read data strobe. In the advanced mode for a data write, the input data is presented by the controller synchronously with a selected edge of both the write data strobe and the read data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

A lithographic method and apparatus used to pattern an object. An illumination system supplies a beam of radiation. An array of individually controllable elements patterns the beam. The patterned beam is projected by a projection system on to a substrate supported on a substrate table. Individual elements of the array are periodically addressed to load an image frame on to the array appropriate to the pattern to be imparted to the beam at any given instant in time taking into account the image to be projected onto the substrate. In any given frame loading operation, only those individual controllable elements that must change state are addressed to reduce the amount of data required to be transferred during the frame loading operation.

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe and also a write data strobe that is out-of-phase relative to the read data strobe, and presents data synchronously with one of the edges of that read data strobe. In the advanced mode for a data write, the input data is presented by the controller synchronously with a selected edge of both the write data strobe and the read data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Software Managed Manycore (SMM) architectures with scratch pad memory for reach core are a promising solution for scaling memory. In these architectures the code and data of the tasks mapped to the cores is explicitly managed by the compiler and often require inter-procedural information and analysis. But, a call graph of the program does not have enough information, and the Global CFG has too much information. Most new techniques informally define and use GCCFG (Global Call Control Flow Graph)—a whole program representation that succinctly captures the control-flow and function call information—to perform inter-procedural analysis. Constructing GCCFGs for several cases in common applications. The present disclosure provides unique graph transformations to formally and correctly construct GCCFGs for optimal compiler management of manycore systems.

A wireless mobile device comprising a tuner for converting a received radio frequency signal to a base band signal or intermediate frequency signal and providing the base band signal or intermediate frequency signal to a receiver, wherein the receiver is arranged to provide received data associated with the base band signal or intermediate frequency signal to an application processor for storage in memory, wherein the application processor is arranged to extract the data from memory in an interleaved form and perform error correction on the interleaved data.

The present invention suggests a storage system capable of realizing highly reliable data back-up. The storage system includes: a first disk array apparatus for providing first volumes for storing data sent from a host system; a second disk array apparatus for providing second volumes for storing back-up data of the first volumes; and a console terminal for operating the first disk array apparatus. The console terminal is equipped with a setting unit for setting a priority for each first volume in accordance with an external command. The first disk array apparatus is equipped with: a storage unit for storing the priorities set by the priority setting unit; and a transfer unit for reading the priorities from the storage unit upon receiving the data and transferring the data stored in the first volumes to the second volumes of the second disk array apparatus in order of descending priority of the first volumes that store the data.

A system and method, called ADD (adaptive data descriptor) and FP (functional proximity), optimizes data transfer between inbound and outbound streams for TCP or other data transfer mechanisms. ADD minimizes data copying in the steam mode, while allowing simultaneous reading from the inbound stream, and writing into the outbound stream from a stored file. ADD and FP jointly minimize total latency in stream-mode data transfer, with or without caching, over multi-core computing systems.

FP assigns processes in a multi-core computing system to minimize cache misses and cache access in shared on-chip caches. FP also assigns threads in a TCP splicing box that provides TCP splicing between a plurality of senders and a plurality of receivers, by assigning one thread or 2 threads per TCP connection. The threads are assigned to thread groups so that each thread group is assigned to a single CPU or core. This assignment maximizes cache hits in shared on-chip caches in a multi-core computing system.

A method for authenticating access to a secured chip SC by a test device TD, the test device storing at least one common key CK and one test key TK, the secured chip SC storing the same common key CK and a reference digest F(TK) resulting from a cryptographic function on the test key TK, the method comprising the steps of:—receiving, by the test device TD, a challenge R produced by the secured chip SC,—combining, by the test device TD, the received challenge R with the test key TK by applying a bidirectional mathematical operation (op), encrypting the result (TK op R) with the common key CK, obtaining a cryptogram CK(TK op R),—sending the cryptogram CK(TK op R) to the secured chip SC—decrypting, by the secured chip SC, the cryptogram CK(TK op R) with the common key CK, obtaining an image key TK′ representing the test key TK by applying, with the challenge R, the reverse operation (op-1) of the mathematical operation (op) previously used by the test device TD,—calculating an expected digest F(TK′) of the image key TK′ with a cryptographic one-way function,—verifying validity by comparing the expected digest F(TK′) with the reference digest F(TK),—if the result of the comparison between the digest F(TK′) of the image key TK′ and the reference digest F(TK) is positive, accessing, by the test device TD, the secure chip SC in a test mode.

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Disclosed is a method and device for testing coins which are placed in a coin acceptor unit and which are displaced in front of an image sensor consisting of lines and columns, whereby said image sensor records an image of the coins that are to be tested. At least one of the front columns in the direction of movement of said coins and/or at least one line of the image sensor captures parameters, which in conjunction with the temporal detection information, are used to provide information on the movement of said coins. It is determined independently from said parameters when the coin will appear in a desired overlap area for recording, whereby the image sensor is shifted into an activation mode of the columns and lines of the overlap area and recording is triggered.