193results about How to "Eliminate charge" patented technology

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read / write circuits in parallel has features to reduce power consumption during read, and program / verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program / verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

There present invention relates to a method for managing the automatic provision of a subscriber network identifier from a central network server to a subscribed communication device, the method comprising receiving notification at the central server relating to a change in the current location for the subscribed device, and determining from the notification whether a new subscriber network identifier is to be provisioned from the central server. The method further comprises selecting a subscriber network identifier on the basis of the current location, if the determining step has determined that a new subscriber network identifier is to be provisioned, and outputting the selected subscriber network identifier for transmission to the subscribed device. The present invention also relates to managing the automatic connection of a subscribed communication device to a network, where a preferred network and preferred subscriber network identifier may be used.

A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method / structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source / drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source / drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method / structure provides for connecting compensating conductors through a series device.

There is provided a circuit for driving a current mode light modulating device. The circuit includes (a) a capacitor for storing a data voltage, (b) a field effect transistor (FET) controlled by a signal on a scan line, for coupling the data voltage from a signal line to the capacitor, and (c) a current source, controlled by the stored data voltage, for driving the device with current provided from a power line. The power line is in a plane that is geometrically parallel to a plane within which the scan line is located.

An apparatus for selectively activating a component on a computing device includes an authorization server that authorizes activation of a component on a computing device in response to an activation request, a component management module that activates the component in response to receiving authorization from the authorization server, and a tracking system that receives transaction data corresponding to the component in response to activating the component. The apparatus may also include a billing system that charges a customer account in response to activation of the component. In certain embodiments, the component management module includes a detection module that requests component activation in response to detecting an increased computing load on the computing device. The detection module may also request component deactivation in response to detecting a decreased computing load on the computing device. Thus the present invention integrates dynamic adjustment of computing power with secure transactions and automatic billing.

The invention provides an electric potential sensor including, at least one detection electrode arranged for capacitive coupling with a sample under test and for generating a measurement signal, and a sensor amplifier adapted to receive the measurement signal as input and to supply an amplified detection signal as output. An input impedance enhancing element provides a high input impedance to the sensor amplifier for increasing the sensitivity of the electrode to reduced electric potentials, and a feedback element applies a coherent feedback signal to the input of the sensor amplifier for enhancing the signal to noise ratio of the sensor.

The present invention teaches methods and systems for subscriber blocking of unauthorized network traffic in a cable data network. The cable modem termination system (CMTS) incorporates a data gateway agent that filters unauthorized traffic thereby eliminating consumption based subscribers from being responsible for related service charges. Embodiments incorporate the use of packet filtering, hybrid stateful packet filtering, content filtering, application layer filtering and time based filtering. Greater acceptance of consumption based billing is achieved by having the filter settings directed by the subscriber.

A light emitting apparatus includes a pixel circuit and a driving circuit which drives the pixel circuit. The pixel circuit includes: a driving transistor which generates a driving current; a light emitting device that determines gradation depending on the driving current; a light emission control transistor; a discharge transistor; a capacitor device; and a first switching device interposed between a gate and a drain of the driving transistor.

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read / write circuits in parallel has features to reduce power consumption during read, and program / verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program / verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

An apparatus for selectively activating a component on a computing device includes an authorization server that authorizes activation of a component on a computing device in response to an activation request, a component management module that activates the component in response to receiving authorization from the authorization server, and a tracking system that receives transaction data corresponding to the component in response to activating the component. The apparatus may also include a billing system that charges a customer account in response to activation of the component. In certain embodiments, the component management module includes a detection module that requests component activation in response to detecting an increased computing load on the computing device. The detection module may also request component deactivation in response to detecting a decreased computing load on the computing device. Thus the present invention integrates dynamic adjustment of computing power with secure transactions and automatic billing.

Sheets fed out of a cassette supporting the sheets by a pickup roller are separated and fed by a sheet separation feeding unit having a feed roller and a separating roller which is rotatable in a direction opposite to a sheet feeding direction. A charge eliminating mechanism for eliminating charges of the separating roller is arranged on the upstream side in the sheet feeding direction in a separation nip portion between the feed roller and the separating roller.

The representative configuration of an image reading unit according to the present invention and an image forming apparatus comprising the same is an image reading unit comprising a document feeding unit, a lamp and a mirror for reading out the image on a document, a flow reading platen provided between the document feeding unit, and the lamp and the mirror for guiding the document while sliding the same against the surface, and an aluminum sheet for grounding the flow reading platen, wherein the aluminum sheet is conductive with the flow reading platen on the document feeding direction upstream side with respect to the document reading position for reading the image in the substantially entire document width by the lamp and the mirror.

Improved methods and preparations are provided for ocular administration of therapeutic drugs. The preparations include respective quantities of a drug and a peptide which enhances transport of the drug across ocular tissues. The drug and peptide components may be separately administered or used as a mixture. The preferred peptide is NC-1059 (SEQ. ID NO. 1).

In an image forming apparatus, an AC bias is supplied to a conveyance belt, and the amount of charge on the printing side of a recording sheet is decreased. The charge of positive polarity and the charge of negative polarity which are different from each other are generated on the printing side of the sheet, so that both the charges are cancelled by each other and the charge on the printing side of the sheet is eliminated. Moreover, the charge eliminator eliminates the charge on the printing side of the sheet by the time the sheet is electrostatically attached to the conveyance belt and conveyed to a position where the sheet confronts the head.

Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

A capacitor switch including a power contactor and an impedance contactor located within a relatively slender container filled with dielectric gas. The container may be a “dead tank” or an insulator. For the insulator configuration, the switch also includes a conductive cap housing a charging impedance located on the end of the insulator. The power contactor includes a relatively fixed probe contact and a linearly moving socket. The impedance contactor is ring-type butt contactor surrounding the penetrating contactor that includes a retracting (but otherwise fixed) contact that surrounds the fixed probe, and a traveling ring contact that surrounds and moves with the moving socket contact. The impedance contactor closes before the power contactor on the closing stroke to introduce the charging impedance into the circuit. A puffer mechanism retards the expansion of the retracting contact on the opening stroke, which causes the impedance contactor to open before the power contactor.

A memory circuit and method to improve signal margin is disclosed. The circuit includes a memory array arranged in rows 702, 704, 706 and columns 750, 752 of memory cells. Each row of memory cells is connected to a respective wordline. Each column of memory cells is connected to one of a bitline and a complementary bitline. An active wordline accesses a respective row of memory cells. The memory circuit includes a plurality of precharge circuits 724, 726, 728. Each precharge circuit is connected to a respective column of memory cells and coupled to receive a precharge signal PRE. An active precharge signal renders a respective precharge circuit conductive. A control and decode circuit 700 changes an inactive wordline signal to an active wordline signal while the precharge signal is active.