61results about How to "Minimize bandwidth" patented technology

A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter / modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I / Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I / Q data signals.

A method and apparatus for segmenting and forwarding data packets received in a communication switch is presented. The method begins by receiving a packet that includes a destination that determines forwarding parameters. As the packet is being received, segmentation cells are created from portions of the packet received where each segmentation cell is provided to a switching fabric as soon as creation of the segmentation cell is completed. When an end portion of the packet is received, verification of proper receipt of the packet is performed. When it is determined that the packet has been received successfully, a verification data set is generated based on segmentation cells that have been utilized to forward the packet. If it is determined that the packet has not been successfully received, a purging data set is generated instead of the verification data set.

The present invention provides a method, computer-readable medium and device for dynamically managing allocation of bandwidth in a packet network using a Dynamic Setting Scheme (DSS) for Class Based Queuing (CBQ). The method includes the steps of maintaining a minimized reserved portion of bandwidth to minimize delay jitter and maximizing a shared portion of bandwidth to maximize overall bandwidth utilization. Allocation of bandwidth may be based on a sharing tree hierarchical scheme that provides for temporary borrowing of bandwidth by real-time applications from bandwidth of non-real-time applications and blocks borrowing of bandwidth by non-real-time applications from bandwidth of real-time applications. DSS typically provides for using measurable parameters, such as queue length and number of borrowing attempts per a predetermined length of time / observation window, as control triggers for implementing adjustment of bandwidth allocation. In one embodiment, the steps include measuring a predetermined parameter at predetermined observation window times and dynamically adjusting allocated bandwidth for parent classes of real-time traffic by adjusting an average of the predetermined parameter to have a value within a predetermined stable region.

Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.

A method of tagging signals for leakage detection and measurement in cable television networks which uses additional signals carrying the tagging information and transmitted in these networks. A narrowband tagging signal or signals are placed in the unused frequency spectrum parts of any used cable television channel, in particular in the guard bands (GB) of analog or digital channels, carrying, for example, television, radio or data services.

A communication network element (536) comprises a transmitter (535) for transmitting at least one timing data packet to at least one further network element (524) over both a first communication link and a second communication link and a receiver (537) for receiving two timing data packets from the at least one further network element (524) over the second communication link. The communication network element (536) further comprises signal processing logic (538) operably coupled to the transmitter and receiver and arranged to calculate a transit delay of the at least one timing data packet over the first communication link based on the received two timing data packets from the at least one further network element (524) over the second communication link, wherein the signal processing logic (538) is capable of scheduling at least one transmission across the first communication link to the at least one further network element (524) in response thereto.