72results about How to "Fabrication yield can be improved" patented technology

A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

A fuel injector which may be employed in injecting fuel into an internal combustion engine. The fuel injector includes an injector body and a head body formed to be separate from the injector body. The head body has installed therein a fuel pressure sensor working to measure the pressure of fuel in the fuel injector and is joined detachably to the injector body. The fuel injector alternatively includes an injector body and a fuel pressure-sensing unit equipped with a fuel pressure sensor. The fuel pressure-sensing unit is installed detachably on the injector body. This structure provides enhanced productivity of the fuel injector and facilitate the ease of replacement of the fuel pressure sensor.

The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same.

The present invention is intended to solve the following problems with a method for fabricating a substrateless semiconductor package using an adhesive sheet as a temporary fixing supporter. A chip can be displaced from a specified position by pressure during resin encapsulation because the chip is not properly held by the adhesive sheet. If such displacement occurs, the relative positional relationship between the chip and an interconnect to be connected to a specified position in a subsequent wiring step also changes by the displacement of the chip from the specified position. Another problem is that if adhesive deposits occur during peeling of the adhesive sheet and the surface of a package is contaminated with the adhesive deposits, adhesive components left on the surface of the chip can inhibit connection between the interconnect and the chip in a subsequent wiring step. To solve these problems, the present invention provides an adhesive sheet for semiconductor device fabrication that is attached to a substrateless semiconductor chip when the chip is encapsulated with resin. The adhesive sheet includes a base material layer and an adhesive layer. The adhesive layer has a specific adhesion strength and peel strength.