129results about How to "Capacitance" patented technology

By decreasing the threshold voltage shift due to the potential change of the cells adjacent in a word line direction, the reliability of a flash memory can be enhanced. Memory cells of a flash memory are formed in p-type wells of a semiconductor substrate and include gate insulator films, floating gates, high-K insulator films, and control gates (word lines). The floating gates and control gates (word lines) are isolated by high-K insulator films. The plurality of memory cells arrayed in row a direction are isolated by isolation trenches extending in a column direction. In the isolation trenches, a silicon oxide film is embedded. In the silicon oxide film, an air gap is provided. A lower end of the air gap extends near to the bottom of the isolation trench, and its upper end extends further above the upper surface of the high-K insulator film covering the floating gate.

The invention provides a manganese dioxide/carbon nanocomposite and a preparation method and application thereof. The preparation method comprises the following concrete steps: mixing an aqueous solution of permanganate, a carbon carrier and an aqueous solution of a divalent manganese salt; carrying out a reaction to produce a precipitate; and carrying out washing and drying so as to obtain the manganese dioxide/carbon nanocomposite. The preparation method has the advantages of easiness, rapidness, environment friendliness and easy realization of scale-up synthesis. The prepared manganese dioxide/carbon nanocomposite is applicable to a super-capacitor, a metal-air battery and a fuel battery.

Method for sputtering from a dielectric target (9) in a vacuum chamber (2) with a high frequency gas discharge, the target (9) being mounted on a cooled metallic back plate (10) and this back plate forming an electrode (10) supplied with high frequency, includes a target thickness (Td) profiled (15) differently over the surface such that in the regions of a desired decrease of the sputtering rate the target thickness (Td) is selected to be greater than in the remaining regions.

A metal contactless smart card includes a first metal layer having a first slit, a second layer, a radio-frequency integrated circuit chip module, and an inlay having an antenna. A nonconductive insert may be fitted in the slit. The first metal layer may include an inlay recess where the inlay may be received and a through-hole where the chip may be inserted. The second layer of the smart card may be made of metal and may also include a slit.

A magnetoinductive flowmeter for measuring the flow rate of a flowing, conductive medium with a capacitive measuring apparatus for detecting empty pipes is provided. In order to improve the detection of empty pipes and, in particular, the capacitive coupling to the medium, the invention provides for the measuring apparatus for detecting empty pipes to comprise a sheet-like electrode in each case and a counterelectrode which form a measurement capacitance C_Mess which is dependent on the medium and on the degree of filling of the measuring tube; for the measuring tube to have a wall thickness which is reduced in order to maximize the measurement capacitance C_Mess at least in the region of the electrode and the counterelectrode; and for the measuring tube to be surrounded by a metal supporting housing, wherein, in order to maintain the pressure resistance of the measuring tube, a hollow-walled supporting body for minimizing the influence of parasitic capacitances on the measurement capacitance C_Mess is arranged in each case in the region of the reduced wall thickness between the electrode and the inner wall of the supporting housing and between the counterelectrode and the inner wall of the supporting housing and supports the measuring tube against the supporting housing in each case.

The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film. In the first wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V are in a relationship of L≧V and in the second wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V is in a relationship of L<V.

The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.

An MR effect element that can obtain the sufficient back flux-guide effect under the condition of reducing the capacitance between the upper and lower electrode layers is provided. The element comprises: an MR effect multilayer provided on the lower electrode layer; an insulating layer surrounding a rear side surface and side surfaces opposed to each other in track width direction of the MR effect multilayer; and an upper electrode layer provided on the MR effect multilayer and the insulating layer, the insulating layer having a concave portion filled with a portion of the upper electrode layer, the concave portion positioned near the rear side surface of the MR effect multilayer, and a bottom point of a concave of the concave portion positioned at the same level or a lower level in stacking direction compared to an upper surface of the free layer.