77results about "Multiprocessor based energy comsumption reduction" patented technology

A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

Disclosed is a method and apparatus for performing tile-based rendering. A sequence of tiles to be processed may be determined based on a locality among the tiles. A tile dispatch unit selects a subsequent tile to be dispatched, based on the determined sequence. The tile dispatch unit may check whether an idle fragment processor exists among the plurality of fragment processors, and may dynamically dispatch the selected tile to an idle fragment processor

A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests. The system also includes a multiprocessor operating system (OS), configured to initially set the second control indicator to enable the VPE to service the interrupts, and further configured to schedule execution of threads on the plurality of TCs, wherein each of the threads is configured to individually disable itself from servicing the interrupts by setting the first control indicator, rather than by clearing the second control indicator.

A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.

A method and apparatus for estimating virtual machine energy consumption, and in particular, a method and apparatus for estimating virtual machine energy consumption in a computer system. The method includes: obtaining system energy consumption of the system hardware resources; obtaining event information of a plurality of functional units into which the system hardware resources are divided, and mapping the event information to the respective virtual machines; and calculating energy consumption of the virtual machines according to a plurality of energy consumption coefficients corresponding to the plurality of functional units and according to the event information mapped to the functional units of the respective virtual machines.

A Resource Manager is provided for managing a plurality of computers. Each of the computers is operable in one of a plurality of power configurations, including a high-power configuration and low-power configurations. The Manager exchanges messages with a Manager Proxy in each computer. Responsive to notifications from Manager Proxies of changes in execution state of an application, the Manager determines a power configuration applicable for the computer of that Manager Proxy, or for a set of computers executing the application. The Manager indicates the power configuration to the Manager Proxy which then decides whether to implement a change.

A method for managing resource allocation in a hierarchical quota system, comprising n layers of quota nodes, n being a positive integer greater than 1, and comprises at a first quota node in an ith layer of quota nodes, in response to receiving a resource allocation request from a user, determining whether an amount of requested resources exceeds a first quota; if the amount of requested resources does not exceed the first quota, determining whether the first node holds a quota delegation for the first quota node; if the first node holds the quota delegation, determining whether the amount of requested resources exceeds a second quota specified by the quota delegation for the first quota node; if the amount of requested resources does not exceed the second quota, allocating the requested resources to the user.

A processor includes an instruction schedule and dispatch (schedule / dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data elements stored in a storage location indicated by a first source operand. The instruction schedule / dispatch unit is to determine a first of the data elements that will not be operated to generate a result written to a destination operand based on a second source operand. The processor further includes multiple processing elements coupled to the instruction schedule / dispatch unit to process the data elements of the SIMD instruction in a vector manner, and a power management unit coupled to the instruction schedule / dispatch unit to reduce power consumption of a first of the processing elements configured to process the first data element.

An electronic device includes a first processor; and a second processor; and a third processor. The second processor is configured to detect an event, select one of the first and third processors to perform one or more operations associated with the event, and cause the selected processor to perform the one or more operations.

An apparatus and system for throttling I / O devices in a computer system is provided. In an example, a method for throttling device power demand during critical power events. The method includes detecting a critical power event and issuing a signal to system devices to defer optional transactions during the critical power event.

A method of processing a computing task required by wireless equipment of a cellular communication network, including classifying the task in at least one class of immediate offloaded execution and a class of immediate local execution, by traversing oriented graph decision nodes and terminal nodes each assigned to one of the classes, the decision nodes being distributed into at least three hierarchical levels themselves distributed into at least three subsets of levels. Traversal of the graph includes: during transit through any decision node of a first subset of levels, verification of a feasibility criterion for the offloading of the task for execution by third-party equipment; during transit through any decision node of a second subset of levels, verification of a criticality criterion for execution of the task, and during transit through any decision node of a third subset of levels, verification of an opportunity criterion for execution of the task.

Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The SoC also determines a thermal gradient for each processing unit to predict a rate at which the processing unit's temperature will change when executing a task. The SoC also monitors a thermal margin of how far each processing unit is from reaching its thermal limit. The SoC minimizes non-uniform heat generation on the SoC by scheduling pending tasks from the task queue to the processing units based on the thermal metrics for the pending tasks, the thermal gradients of each processing unit, and the thermal margin available on each processing unit.