44 results about "Zero-order hold" patented technology

A switched-current oscillator having a dc current source adapted to charge a capacitor so that the capacitor charging time is controlled based on a sequence of (pseudo)randomly selected values, each of those values defining a corresponding charging time. A discharge device is adapted to discharge the capacitor if the voltage across the capacitor reaches a threshold voltage, at which point the next value in the sequence is selected to determine the next charging time. A square-wave clock signal having spread-spectrum characteristics is generated in the oscillator by using the series of charge-discharge cycles corresponding to the sequence of randomly selected values to toggle a flip-flop operating as a delay line and zero-order hold.

A feedforward control system using a polynomial formula not affected by discretization error is realized in a magnetic disk drive. In one embodiment, the magnetic disk drive is intended to move a head for performing at least one of recording and playback to and from a magnetic recording medium to a target position. The feedforward input has a seek control system computed by a polynominal formula of a time function. The coefficients of the polynomial formula have been derived from boundary conditions including the characteristics of a zero-order hold.

In a motor driving device where a motor having a winding wire with small inductance value is driven by a digital control means comprised of control means including a current command value calculating means, a current control means and a PWM control means whose sampling periods are different from each other, when discrete signals sampled by the respective control means are zero-order-held, a motor current includes a lot of higher harmonic waves due to a quantization error, thereby increasing a motor noise.When an n-th-order hold means is provided between the respective control means with different sampling periods, the quantization error can be reduced remarkably, and thus the higher harmonic wave components included in the motor current are reduced, thereby greatly reducing the motor noise.

The invention relates to a remote control robot self-driving sampling system. The system comprises a remote control robot, a sensing mechanism, a data buffer area, a data processing module, a signal generator, a clock module, a central processor module, an execution mechanism, an information display module and a communication module, wherein the sensing mechanism and the execution mechanism are installed on the remote control robot; the data buffer area, the data processing module, the signal generator and the clock module are connected in sequence and then connected with the sensing mechanism; the sensing mechanism comprises a sensor and a camera; the data sampled by the sensing mechanism are transmitted to the central processor module through a communication network; and a control instruction of the central processor module is transmitted to the execution mechanism through the communication network. The execution mechanism is a zero-order holder. The invention also discloses a sampling method of the system. By arranging the data buffer area, the data processing module, the signal generator, the clock module, the central processor module and the like, and by connecting the components with various physical devices reasonably, the self-driving sampling of the remote control robot is realized. The hardware is connected simply; the method for realizing the self-driving sampling is simple, convenient and practicable; the network load can be reduced; and the operation performance of the remote control robot is modified, and thus the system has practical application and population value.

The invention discloses a complex vector PI controller decoupling and delay compensation method of a grid-connected converter. Based on the vector model of the controlled object, the zero point of the controller is directly set at the pole of the controlled object to obtain Complex coefficient current controller model; for the one-shot delay of digital control and the inherent zero-order hold characteristic of the converter, the system delay transfer function is calculated, and the current loop is realized by connecting the delay compensation item in series after the complex vector PI controller delay compensation. The invention provides a simple and effective method for the current loop design of the grid-connected converter, suppresses the current coupling problem of d and q axes of the current loop to the greatest extent, increases the phase angle margin of the system through delay compensation, and improves the current Ring stability and improved dynamic response performance.

The invention belongs to the technical field of integrated circuit design modeling, particularly discloses an s-domain model of an integrated frequency-modulated continuous wave digital frequency synthesizer, and provides a frequency-based modeling method. By using an accumulator model, a pulse switch, a charge pump and an on-chip capacitor are modeled; through the combination of an analog integrator, an ideal sampler, a zero-order retainer, a quantizer and a differentiator, a digital frequency converter is modeled, so that the prediction accuracy of the model is greatly improved; a normalized gain module expression is deduced, so that the model can carry out accurate prediction only by virtue of the accuracy of time-to-digital converter, loop bandwidth and crystal frequency during frequency error and phase noise prediction. The s-domain model can accurately predict the frequency error of a frequency-modulated continuous wave produced by the frequency synthesizer, and the phase noise of dot frequency.

The invention provides a duty cycle conversion circuit and method. The method comprises the following steps: charging a charging capacitor with a charging current when a PWM (Pulse-Width Modulation) signal is at high level; stopping charging when the PWM signal is at low level; transferring the voltage from the charging capacitor to an output capacitor and then converting to obtain a simulating signal; recovering the electric quantity in the charging capacitor into initial voltage; cycling in sequence until the PWM signal in each cycle is converted into the simulation signal before the cycle is ended. The duty cycle conversion method has the characteristics that the respond speed is fast, the converted simulating signal is able to remain zero order, and the problem of large ripple wave caused by insufficient filter depth of the converting circuit in the prior art is avoided; in addition, the large-capacity energy storing element in the traditional converting circuit is removed, thus the chip integration can be performed conveniently, the size of an electronic device and the manufacturing cost can be reduced, and the service life is also prolonged as the same time.

The invention discloses a slide form control method, system and device based on a Markov jump system and a computer readable storage medium. The system comprises a controlled system, a sensor, a firstevent detector, a first zero-order holder, an observer, a second event detector, a second zero-order holder and the closed loop Markov jump system of a controller, and the controlled system, the sensor, the first event detector, the first zero-order holder, the observer, the second event detector, the second zero-order holder and the closed loop Markov jump system of the controller satisfy a preset stable condition; according to the stable condition, a first positive weighting matrix preset in the first event detector is larger than 0, a second positive weighting matrix preset in the first event detector is larger than 0, a positive definite matrix is larger than 0, and a matrix carrying unknown and known conditions of the transition probability is considered. According to the slide formcontrol method, system and device based on the Markov jump system and the computer readable storage medium, by presetting the stable condition in which the unknown and known conditions of the transition probability of the controlled system are considered, the overall system is more stable; meanwhile, through the event detectors, the communication frequency of the overall system is reduced, and blockage of an information channel is avoided; the observer can observe the state of unknown states in the controlled system, so that the controlled system also runs more stably.

The invention discloses a modeling and analyzing method for a switching power converter controlled by a digital current mode. The method comprises the steps of (100) adopting a state-space averaging method to build a transfer function of a power level circuit of the switching power converter; (200) listing and writing a transfer function of a zero-order holding circuit of a digital controller and a delay delivery function of a digital control loop; (300) listing and writing a detection gain of an output voltage and a detection gain of an inductive current, wherein the detection gains comprise A / D conversion gains; (400) obtaining a function Gc representing a current control law according to a digital current mode control law, designing a voltage loop compensator Gv on this basis, and completing modeling of a whole switching power converter system controlled by the digital current mode; (500) finally adopting an equivalent small parameter method to conduct stability analysis on the built model. According to the modeling and analyzing method, the accuracy of the system model is improved, and the quite high application value is obtained for research on system nonlinearity.

The invention discloses an optimal-design-based variable sampling rate re-sampling method, which comprises the following steps of: first over-sampling an input discrete signal, namely, performing L-fold interpolation on the input discrete signal by using an L-fold interpolation filter; then recovering the discrete signal into a continuous signal by using a zero-order holding filter; and finally re-sampling the continuous signal according to conversion requirements. The method has the advantages that: high calculation accuracy and lower calculated amount are ensured; the method is fully digital and discrete; only multiplication and addition operations are required, and typical digital signal processing convolution calculation is performed; the hardware accelerated calculation capability of a digital signal processor (DSP) can be fully utilized; and the various protected data re-sampling requirements are met.