38 results about "Single event latchup" patented technology

A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.

Method and system for Single Event Latchup (SEL) current surge mitigation involves monitoring data signals for a protected device and deriving from them a detected signature comprised of one or more detected signature vector components. The detected signature vector components are compared to previously stored signature vector components. Based on the comparing, the system selectively differentiates between the occurrence of standard power surges associated with normal operation of the protected device, and a non-standard current surge which requires cycling power of the protected device for continued proper functioning of the protected device.

A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source / drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source / drain material for the NMOS device and a second metal source / drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

A system for mitigating a solid state power controller (SSPC) open or closed state change caused by single event latchup (SEL) includes an ON circuit, an OFF circuit operatively connected in parallel to the ON circuit, a holding capacitor operatively connected in parallel with the ON circuit and the OFF circuit, and a power switching device operatively connected to the holding capacitor and the ON circuit. The system is configured to maintain, during and after the SEL, a drive state voltage to the power switching device that is stored in the holding capacitor prior to the SEL.

The invention relates to a low drop-out overcurrent protection circuit with controllable output. The overcurrent protection circuit comprises a main path, an auxiliary path, a reverse voltage protection circuit, a main and auxiliary path overcurrent switching and enabling inhibit control circuit, an efficiency adjustment resistor, an overcurrent sampling resistor and a limited current setting circuit; the overcurrent protection circuit has the functions of automatic overcurrent protection and output enabling / forbidding, is connected to a power entrance of a circuit in series, and can realize the functions of single event latchup resistance of satellite-bone equipment components and short circuit overcurrent protection of the circuit, thus having high practical value. The special application specific integrated circuit (ASIC) chip customized according to the low drop-out overcurrent protection circuit with controllable output well meets the application demands of satellite-bone equipment of a spacecraft and is beneficial to improvement of the equipment integration level; furthermore, the circuit overcurrent protection also has very strong universality for circuits besides the spacecraft.