38 results about "Single event latchup" patented technology

A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.

A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source / drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source / drain material for the NMOS device and a second metal source / drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

A method for testing an integrated circuit for potential latchup sites includes applying a voltage to the integrated circuit, measuring a current through the integrated circuit, applying at least one radiation beam to at least one area of the integrated circuit, and detecting an occurrence of a latchup by detecting an increase of the current through the integrated circuit upon applying the at least one radiation beam to the at least one area of the integrated circuit.

Method and system for Single Event Latchup (SEL) current surge mitigation involves monitoring data signals for a protected device and deriving from them a detected signature comprised of one or more detected signature vector components. The detected signature vector components are compared to previously stored signature vector components. Based on the comparing, the system selectively differentiates between the occurrence of standard power surges associated with normal operation of the protected device, and a non-standard current surge which requires cycling power of the protected device for continued proper functioning of the protected device.

A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source / drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source / drain material for the NMOS device and a second metal source / drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.

A system for mitigating a solid state power controller (SSPC) open or closed state change caused by single event latchup (SEL) includes an ON circuit, an OFF circuit operatively connected in parallel to the ON circuit, a holding capacitor operatively connected in parallel with the ON circuit and the OFF circuit, and a power switching device operatively connected to the holding capacitor and the ON circuit. The system is configured to maintain, during and after the SEL, a drive state voltage to the power switching device that is stored in the holding capacitor prior to the SEL.

The invention relates to a low drop-out overcurrent protection circuit with controllable output. The overcurrent protection circuit comprises a main path, an auxiliary path, a reverse voltage protection circuit, a main and auxiliary path overcurrent switching and enabling inhibit control circuit, an efficiency adjustment resistor, an overcurrent sampling resistor and a limited current setting circuit; the overcurrent protection circuit has the functions of automatic overcurrent protection and output enabling / forbidding, is connected to a power entrance of a circuit in series, and can realize the functions of single event latchup resistance of satellite-bone equipment components and short circuit overcurrent protection of the circuit, thus having high practical value. The special application specific integrated circuit (ASIC) chip customized according to the low drop-out overcurrent protection circuit with controllable output well meets the application demands of satellite-bone equipment of a spacecraft and is beneficial to improvement of the equipment integration level; furthermore, the circuit overcurrent protection also has very strong universality for circuits besides the spacecraft.

The invention relates to a D flip-flop with a set terminal. The D flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module is used for outputting corresponding data signals to a data output module according to clock signals output from the clock module and external data signals received through the delay filtering module. The master-slave DICE latch module is provided with the set terminal; the delay filtering module is used for preventing transient pulses caused by a single event effect from entering inside a register; the master-slave DICE latch module is used for correcting internal node upsetting caused by the single event effect; the set terminal is used for setting an output terminal to be 1; the delay filtering module plays a role in resisting SET (Single Event Transient), the master-slave DICE latch module is used for preventing internal storage nodes from upsetting and plays a role in resisting SEU (Single Event Upset), and a guard band structure is added during layout designing, is used for effectively inhibiting SEL (Single Event Latchup) and is also beneficial to the reduction of SET pulse width in a circuit.