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D flip-flop with set terminal

A trigger, set technology, applied in the direction of pulse generation, electrical components, generation of electrical pulses, etc., can solve problems such as affecting subsequent operations, adverse system work, system errors or crashes

Active Publication Date: 2015-07-29
NO 47 INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The D flip-flop with a set terminal is the most commonly used sequential device in integrated circuits. This device will retain error information after a single-event flip and a single-event transient pulse, affecting subsequent operations, resulting in errors in the entire system or crash with serious consequences
In addition, the traditional D flip-flop with a set terminal will show an unstable state after power-on, which is not conducive to the system work

Method used

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  • D flip-flop with set terminal

Examples

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Embodiment Construction

[0031] Below in conjunction with accompanying drawing, invention is described in further detail.

[0032] Such as figure 1 As shown, the D flip-flop with a set terminal in an embodiment of the present invention includes a clock module 1 , a delay filter module 2 , a master-slave DICE latch module 3 , and an output module 4 . The master-slave DICE latch module includes a master module 31 and a slave module 32, both of which are DICE reinforced, and a delay filter module 2 is added to the data end.

[0033] The clock signal output of the clock module 1 is connected to the clock signal input of the master-slave DICE latch module 3, the data input of the delay filter module 2 is connected to the data source, and the data output is connected to the master-slave DICE latch The data input end of the module 3 is connected, and the data output end of the master-slave DICE latch module 3 is connected to the signal input end of the output module 4 .

[0034] The master-slave DICE latch...

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PUM

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Abstract

The invention relates to a D flip-flop with a set terminal. The D flip-flop comprises a clock module, a delay filtering module, a master-slave DICE latch module and an output module, wherein the master-slave DICE latch module is used for outputting corresponding data signals to a data output module according to clock signals output from the clock module and external data signals received through the delay filtering module. The master-slave DICE latch module is provided with the set terminal; the delay filtering module is used for preventing transient pulses caused by a single event effect from entering inside a register; the master-slave DICE latch module is used for correcting internal node upsetting caused by the single event effect; the set terminal is used for setting an output terminal to be 1; the delay filtering module plays a role in resisting SET (Single Event Transient), the master-slave DICE latch module is used for preventing internal storage nodes from upsetting and plays a role in resisting SEU (Single Event Upset), and a guard band structure is added during layout designing, is used for effectively inhibiting SEL (Single Event Latchup) and is also beneficial to the reduction of SET pulse width in a circuit.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a D flip-flop with a set terminal. Background technique [0002] When a semiconductor device is in a radiation environment, the surrounding energy particles will penetrate into the chip and generate ionizing radiation, which will generate a certain number of electron and hole pairs on the trajectory of the energy particles. These electrons and holes generated by the ionizing radiation of single energy particles may be absorbed by the internal nodes of the circuit under the action of the electric field, resulting in abnormal function of the semiconductor device. These effects are called single event effects. [0003] A single event effect is a random effect. In 1975, people discovered the abnormal flip phenomenon of Binder, communication satellites, and JK triggers. After continuous research, it was found that the factors that caused the abnormal flip phenomenon included hig...

Claims

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Application Information

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IPC IPC(8): H03K3/356
Inventor 孙大成陈智王爽
Owner NO 47 INST OF CHINA ELECTRONICS TECH GRP
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