A kind of d flip-flop with clear terminal

A technology for clearing terminals and flip-flops, which is applied in the direction of pulse generation, electrical components, and electric pulse generation, and can solve problems such as system errors or crashes, unstable D flip-flops, and unfavorable system work.

Active Publication Date: 2017-07-07
NO 47 INST OF CHINA ELECTRONICS TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

D flip-flop is the most widely used sequential device in integrated circuits. After single-event flipping and single-event transient, this kind of device will retain the error information and affect the subsequent operation, which will lead to the error or collapse of the entire system and cause serious damage. s consequence
In addition, the traditional D flip-flop will show an unstable state after power-on, which is not conducive to the system work

Method used

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  • A kind of d flip-flop with clear terminal
  • A kind of d flip-flop with clear terminal
  • A kind of d flip-flop with clear terminal

Examples

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Embodiment Construction

[0030] Below in conjunction with accompanying drawing, invention is described in further detail.

[0031] like figure 1 As shown, a D flip-flop with a reset terminal according to an embodiment of the present invention includes a clock module 1 , a delay filter module 2 , a master-slave DICE latch module 3 , and an output module 4 . The master-slave DICE latch module includes a master module 31 and a slave module 32 . Both the master and slave stages are reinforced with DICE, and a delay filter module 2 is added to the data end.

[0032] The clock signal output of the clock module 1 is connected to the clock signal input of the master-slave DICE latch module 3, the data input of the delay filter module 2 is connected to the data source, and the data output is connected to the master-slave DICE latch The data input end of the module 3 is connected, and the data output end of the master-slave DICE latch module 3 is connected to the signal input end of the output module 4 .

[...

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Abstract

A D flip-flop with a clearing terminal, including a clock module, a delay filter module, a master-slave DICE latch module, and an output module; wherein the master-slave DICE latch module is based on the clock signal output from the clock module, and Output the corresponding data signal to the data output module through the external data signal received by the delay filter module. The master-slave DICE latch module is provided with a clearing terminal; the delay filter module is used to prevent the transient pulse caused by the single event effect from entering the register; the master-slave DICE latch module is used to correct the transient pulse caused by the single event effect. The internal node flips; the clearing terminal is used to set the output terminal to zero; the delay filter module plays the role of anti-SET, and the master-slave DICE latch module prevents the internal storage node from flipping and plays the role of anti-SEU. A guard band structure is added to the layout design, which effectively suppresses the SEL and also helps to reduce the SET pulse width in the circuit.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a D flip-flop with a reset terminal. Background technique [0002] When a semiconductor device is in a radiation environment, the surrounding energy particles will penetrate into the chip and generate ionizing radiation, which will generate a certain number of electron and hole pairs on the trajectory of the energy particles. These electrons and holes generated by the ionizing radiation of single energy particles may be absorbed by the internal nodes of the circuit under the action of the electric field, resulting in abnormal function of the semiconductor device. These effects are called single event effects. [0003] A single event effect is a random effect. In 1975, people discovered the abnormal flip phenomenon of Binder, communication satellites, and JK triggers. After continuous research, it was found that the factors that caused the abnormal flip phenomenon included h...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/3562
Inventor 陈智王爽
Owner NO 47 INST OF CHINA ELECTRONICS TECH GRP
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