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Memory with single-event latchup prevention circuitry

A technology of single-event locking and memory cells, which is applied in the field of integrated circuits and integrated circuit memory components, and can solve problems such as damaging devices and circuit failures

Active Publication Date: 2018-06-26
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When this happens, the lockup can cause circuit failure or possibly destroy the entire device

Method used

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  • Memory with single-event latchup prevention circuitry
  • Memory with single-event latchup prevention circuitry
  • Memory with single-event latchup prevention circuitry

Examples

Experimental program
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Embodiment Construction

[0020] Embodiments of the invention relate to integrated circuit memory elements that may be subject to single event lock-up (SEL). According to an embodiment, an SEL prevention circuit is provided that detects a lock signal using a sense amplifier. In response to detecting the lockout signal, drivers in the SEL prevention circuit can then force the n-well within the memory element into a deep reverse biased region to temporarily turn off any parasitic components that may have turned on during single event lockup. In another suitable arrangement, the n-well of the memory element may be constantly biased to an elevated voltage level to permanently turn off the parasitic components to completely eliminate latch-up.

[0021] It will be appreciated by those skilled in the art that the present exemplary embodiment may be practiced without some or all of these specific details. In other instances, well known operations have not been described in detail in order not to unnecessarily...

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Abstract

Provided is an integrated circuit. The integrated circuit includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.

Description

Background technique [0001] This application relates to integrated circuits, and more particularly, to integrated circuits including memory. [0002] Integrated circuits often contain volatile memory elements. Volatile memory elements retain data only while the integrated circuit is powered. If power is lost, the data in the volatile memory elements will be lost. While non-volatile memory elements such as those based on Electrically Erasable Programmable Read-Only Memory technology do not lose data in this way, manufacturing non-volatile memory elements that are part of a given integrated circuit is often not expected or impossible. [0003] Therefore, volatile memory elements are often used. For example, static random access memory (SRAM) chips contain SRAM cells, which are a type of volatile memory element. In programmable logic device integrated circuits, SRAM cells can be used as configuration random access memory (CRAM) cells. A programmable logic device is an integ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/24G11C11/417
CPCG11C7/24G11C11/417G11C11/4125H01L27/0921G11C5/14
Inventor 张卫民徐彦忠
Owner INTEL CORP
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