42 results about "Linear temporal logic" patented technology

Provided is a single mobile robot optimal itineration control method based on a target tracking control strategy. The method comprises seven steps of map construction, task description, topology construction, optimal path searching, task decomposition, target tracking control, and pose information feedback. The method comprises: firstly, based on a linear temporal logic theory, combining a constructed weighting switching system and a linear temporal logic task formula, establishing task feasible network topology; then, using an optimal path searching method based on a Dijkstra algorithm to search an optimal path, and storing discrete coordinate points in environment corresponding to the optimal path in cache, and sending the discrete coordinate points to a target tracking controller in order; then, using a target tracking control method to give a controlled quantity to control a robot to move to a target point according to distance between the robot and the target point and deviation of angles; and finally, in an operation process of the robot, using a global camera to acquire present position coordinate and orientation information of the robot in real time, and feeding back to the target tracking controller, so as to realize closed-loop control.

The invention discloses an LTL-A*-A*optimal path planning method applicable to dynamic environment. The advantage of meeting complex mission requirements in actual application of linear temporal logic (LTL) and the advantage of being high in search efficiency of the A*algorithm are combined, and the method mainly includes LTL-A*global path optimization and local path optimization based on the A*algorithm. First, the optimal path meeting the task requirement in the environment is partially searched out through LTL-A*global path optimization; then, a robot tracks the global optimal path obtained through searching and detects environment information; finally, when local environment changes, a part segment in the global optimal path cannot continue allowing passage, the local optimal path is searched for by adopting the A*algorithm, the segment not allowing passage is bypassed, and operation continues along the global optimal path to complete an appointed task.

Time-course data with an underlying causal structure may appear in a variety of domains, including, e.g., neural spike trains, stock price movements, and gene expression levels. Provided and described herein are methods, procedures, systems, and computer-accessible medium for inferring and/or determining causation in time course data based on temporal logic and algorithms for model checking. For example, according to one exemplary embodiment, the exemplary method can include receiving data associated with particular causal relationships, for each causal relationship, determining average characteristics associated with cause and effects of the causal relationships, and identifying the causal relationships that meet predetermined requirement(s) as a function of the average characteristics so as to generate a causal relationship. The exemplary characteristics associated with cause and effects of the causal relationships can include an associated average difference that a cause can make to an effect in relation to each other cause of that effect.

The invention discloses a method for removing memory thrashing through the efficient LTL ((Linear Temporal Logic) model detection of a large-scale system. A LHS (Linear Hash Storage) algorithm is adopted to mainly aim at quickly finding a Hash value stored in a Hash table in a disk; no matter whether the classification of the Hash table in the memory is empty or not, the Hash table can be stored in an external memory and is processed by a new technology after being stored in the external memory, and the complexity of I/O is a linear size which is the same with the Hash table; and a CDD (Cached Duplicate Detection) technology permits a duplicate in the memory to be detected through effective access, duplicate detection complexity can be lowered through the LHS and the CDD, the plan of DPM (Dynamic Path Management) enables two nested depth-first stacks to dynamically share a memory cell, and the memory thrashing problem can be solved through the effective management of the stack and the state, wherein the memory thrashing means that the frequent movement of the state in the memory may obviously increase I/O operation frequencies so as to lower the efficiency of the algorithm.

A method includes enabling a robot to learn a mapping between English language commands and Linear Temporal Logic (LTL) expressions, wherein neural sequence-to-sequence learning models are employed to infer a LTL sequence corresponding to a given natural language command.

The invention discloses a CPS rare event probability prediction method based on statistical model inspection. The system is based on a statistical model inspection method and is composed of a samplingmonitor, a protocol verifier and a probability predictor. The method comprises the specific implementation steps that a sampling monitor adopts an importance random sampling algorithm to randomly sample and generate a CPS system state feature sequence described based on a hybrid automaton; a protocol verifier based on linear temporal logic can generate a system visible characteristic state sequence and a verification result corresponding to protocol satisfaction, and the verifier can take the verification result as a training sample set of a probability predictor based on an HMM implicit Markov model; on the basis of sufficient sample set learning, the probability predictor calculates the probability that the subsequent state of the system is a rare event state, and outputs the result, inaddition, the method also has the function of correcting the prediction capability of the predictor by using the probability prediction result.

The invention provides a formalized detection method of an intelligent UML (Unified Modeling Language) model and a device. The method comprises the steps of: establishing an UML model for a true system and converting the UML model into an XMI (Extensible Markup Language) model; extracting predetermined element information from the XMI model and converting the predetermined element information semantically to obtain an SMV (Symbolic Modeling Verification) model by applying a set of conversion rule; acquiring an CTL (Complementary Transistor Logic) and/or an LTL (Linear Temporal Logic) propositional logic detection formula, wherein the CTL and/or LTL propositional logic detection formula are/is used for detecting the SMV model; and constructing a binary decision diagram according to the CTL and/or LTL propositional logic detection formula and the SMV model to detect the SMV model so as to obtain a detection result. According to the embodiment disclosed by the invention, the formalized detection method has the advantages of high detection accuracy and wide application, and can comprehensively detect the UML model which has higher demand on safety in a software development process.

The invention discloses a general parallel mining method for linear temporal logic specifications. The method includes the steps of pretreatment, specification case generation, specification case verification and result sieving, wherein during preprocessing, segmentation processing is carried out on a log file to obtain an event set occurring in the log file and collect occurrence position information of events in the log file; during specification case generation, an input specification template is utilized, and in combination with the event set in the log file, detailed linear temporal logic specification cases are generated; during specification case verification, the preprocessed event position information is utilized for calculating the support degrees and confidence coefficients of the specification cases in a log; during result sieving, mined result sets are sieved, and the specification cases with the supporting degrees and confidence coefficients not meeting mining requirements are removed. According to the method, a multi-thread technology is sufficiently utilized for parallel calculation, so that the linear temporal logic specifications of any types are efficiently mined.

The invention provides a train automatic protective system safety analysis method based on system theory hazard analysis, and belongs to the field of train automatic protective system safety engineering. The train automatic protective system safety analysis method comprises the steps: system-level accidents and danger are determined by combing system structure composition and functional logic; a hierarchical control structure block diagram of a system is constructed, a system process module is established, the system control behavior is analyzed, and the danger control behavior is obtained; and how the danger control behavior happens is analyzed, the cause is determined, a danger control scenario is defined, and corresponding safety constraints are formulated to be used in design of the train automatic protective system. The obtained safety constraints described through texts are further subjected to formal representation to be converted into a linear temporal logic language to be added into an SMV criterion model to be verified; and compared with a traditional safety analysis method, fault analysis is wider in covering, analytical effectiveness is higher, and the safety constraints obtained through verification are more effective.

The invention relates to a verification method and system for security protocol formalization, and relates to the technical field of network security, and the method comprises the steps: describing a to-be-verified security protocol, and obtaining a security protocol specification; analyzing the security protocol specification to obtain a protocol configuration object; constructing a protocol model according to the protocol configuration object; constructing an attacker model based on the protocol model, and optimizing the attacker model; describing the security attribute of the security protocol according to the linear temporal logic; and constructing a communication environment based on the optimized attacker model, verifying whether the protocol model meets the security attribute or not through a model detector SPIN in the communication environment, and if not, outputting an attack path by the model detector SPIN. According to the method, modeling can be carried out on different types of security protocols, universality is achieved, the security of the security protocols can be automatically verified, and automation is achieved.

The invention discloses a temporal logic-based microcontroller runtime verification method. The method comprises an event reception step, an event pre-processing step, a user edition step and an LTL verification step, wherein the event reception step indicates receiving an event sequence sent by a microcontroller; the event preprocessing step indicates pre-processing events received in the event reception step, converting the events into independent atomic propositions, establishing one-to-one mapping between variable identifiers and the atomic propositions, and outputting an event sequence character string; the user edition step indicates providing an edition interface for a user so that the user can edit the atomic propositions and an LTL formula; and the LTL verification step indicates verifying whether the execution carried out on the event sequence character string by the microcontroller satisfies the LTL formula input by the user or not. According to the method disclosed by the invention, the real-time verification of microcontrollers can be realized, the possible output spaces of the microcontrollers can be obtained, and certain illegal events can be artificially authenticated.

The invention discloses a multi-party contract signing protocol fairness verification method based on the CSP# and LTL. The method includes the following steps that first, a multi-party contract signing protocol is modeled with the CSP# language; second, the fairness of the protocol is described in a formalized mode through the linear temporal logic (LTL), and the formal description includes state reduction and protocol fairness description; third, model check on a PAT platform is achieved, and fairness verification and a visual attack path are given out. With the method, the fairness can be automatically verified just by inputting a CSP# model of the protocol and the LTL fairness description on the basis of the protocol rules, operation is easy to perform, and the nature of the protocol can be verified practically. A state reduction rule is given for the state space explosion problem, state branch reduction is well completed, and meanwhile, the time and space complexity is reduced. The automatic tracking attack path is given so that the protocol can be improved and competed.

The invention discloses a universal parallel mining system for linear temporal logic specifications. The system comprises a preprocessing module, a specification instance generation module, a specification instance verification module and a result screening module, wherein the preprocessing module performs segmentation processing on a log file, obtains an event set occurring in a log and collects occurrence position information of events in the log; the specification instance generation module generates specific linear temporal logic specification instances in combination with the event set in the log by utilizing an input specification template; the specification instance verification module is in charge of calculating support degrees and confidence degrees of the specification instances in the log by utilizing the preprocessed event position information; and the result screening module is in charge of screening a mined result set to remove the specification instances with the support degrees and the confidence degrees not meeting the mining requirements. According to the mining system, a multithread technology is fully utilized to perform parallel computing, so that any type of the linear temporal logic specification can be efficiently mined.

A method for computer-assisted system design of dynamic systems is described herein. In accordance with one embodiment the method comprises: providing a textual system description; converting, using acomputer, the textual system description into a linear temporal logic LTL formula; converting, using a computer, the LTL formula into a first automaton; providing, using a computer, a second automaton representing the system dynamics; and generating, using a computer, a testing automaton by combining the first and the second automaton.