45results about How to "Long latency" patented technology

A method of testing a digital mobile phone network such as a GPRS or 3 G network comprises creating test traffic using an unmodified test mobile phone coupled to a computer, and using the computer to measure a parameter associated with the network's response to the test traffic. The measurements made by the computer are encoded into the test traffic to create a data stream within the mobile phone network comprising test traffic, measurements relating to the test traffic, and signalling relating to the test traffic, whereby this data stream can be captured at points within the network and analysed to investigate the functioning of the network dynamically as the network is exercised with the test traffic. Software and test equipment for performing the method are also described.

A two-level error control protocol detects errors on the subline level and corrects errors using the codeword for the entire line. This enables a system to read small pieces of coded data and check for errors before accepting them, and in case errors are detected, the whole codeword is read for error correction.

Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory.

A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density.

A SIP client for a communication device includes a user agent to communicate with a user application in the communication device. The user agent provides a high-level application interface to the user application and translates user commands into corresponding signaling and media operations. The same user agent may be shared by a plurality of user applications. A signaling agent controlled by the user agent performs signaling operations necessary to establish and maintain communication sessions. To avoid signaling overhead on a high cost network, the SIP client can be located in a remote network so signaling messages do not need to traverse the high cost network.

A method for changing power states of a computer sends a shutdown event to all running applications before the computer goes to sleep to prevent data loss in a sleep state of the computer. Furthermore, the method stores a system memory image into a flash memory before the computer goes to the sleep state. Moreover, the method restores the system memory image from the flash memory to the system memory when the computer exit the sleep state to come back the work state.

Circuitry speeds up the QR decomposition of a matrix. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. This implementation performs Gram-Schmidt orthogonalization with no dependencies between iterations. QR decomposition of a matrix can be performed by processing entire columns at once as a vector operation. Data dependencies within and between matrix columns are removed, as later functions dependent on an earlier result may be generated from partial results somewhere in the datapath, rather than from an earlier completed result. Different passes through the matrix are timed so that different computations requiring the same functional units arrive at different time slots. After the Q matrix has been calculated, the R matrix may be calculated from the Q matrix by taking its transpose and multiplying the transpose by the original input matrix.

A method for representing a second presentation of audio channels or objects as a data stream, the method comprising the steps of: (a) providing a set of base signals, the base signals representing a first presentation of the audio channels or objects; (b) providing a set of transformation parameters, the transformation parameters intended to transform the first presentation into the second presentation; the transformation parameters further being specified for at least two frequency bands and including a set of multi-tap convolution matrix parameters for at least one of the frequency bands.

A communication load determining apparatus is used for a communication system which includes a plurality of communication devices performing communication via a common bus. The communication system operates in accordance with a communication protocol that defines which a priority order is set to each of the frames transmitted from the communication devices and which a frame having a lower priority has a longer transmission latency before being transmitted to the bus. In the communication load determining apparatus, a low-priority frame having a lower priority than other frames to the bus is transmitted, and a transmission latency of the low-priority frame is measured. The communication load determining apparatus determines whether or not abnormality has occurred in a communication load in the bus on the basis of the measured transmission latency to produce a determination result. The produced determination result is stored.

A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

A hearing device comprises a receiver, an input buffer and a sample processor, the receiver being adapted to receive samples of a digital audio signal and feed received samples as a digital input signal to the input buffer, the sample processor being adapted to process the buffered samples to provide samples of a digital output signal such that the digital output signal is a sample-rate converted representation of the digital input signal with a predetermined target sample rate. The hearing device further comprises a latency controller adapted to estimate the quality of reception of the digital audio signal and to control the processing of the buffered samples in dependence on the estimated quality of reception.

Data communications and storage systems require error control techniques to be transferred successfully without failure. Polar coding has been used as a state-of-the-art forward error correction code for such an error control technique. However, the conventional decoding based on successive cancellation has a drawback in its poor performance and long latency to complete. Because the factor graph of polar codes has a lot of short cycles, a parallelizable belief propagation decoding also does not perform well. The method and system of the present invention provide a way to resolve the issues by introducing a protograph lifting expansion for a polar coding family so that highly parallelizable decoding is realized to achieve a high coding gain and high throughput without increasing the computational complexity and latency. The invention enables an iterative message passing to work properly by eliminating short cycles through a hill-climbing optimization of frozen bits allocation and permutation.