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53 results about "Delay equalization" patented technology

In signal processing, delay equalization corresponds to adjusting the relative phases of different frequencies to achieve a constant group delay, using by adding an all-pass filter in series with an uncompensated filter. Clever machine-learning techniques are now being applied to the design of such filters.

System and method for delay equalization of multiple transmission paths

The present invention provides systems and methods for addressing the effects of non-linear phase response, such as by equalizing electrical delays among transmission paths. A preferred embodiment provides phase detection circuitry and phase adjustment circuitry in the signal paths of a multiple beam or phased array antenna to provide delay equalization of the signal paths. Communication systems implementing the systems and methods of the present invention are provided broadband phase calibration and, therefore, are enabled to provide controlled and predictable beam forming over a broad range of frequencies.
Owner:F POSZAT HU

Group delay equalizer integrated with a wideband distributed amplifier monolithic microwave integrated circuit

A wideband distributed or feedback amplifier monolithic microwave integrated circuit (MMIC) is disclosed that contains an integrated group delay equalizer circuit to compensate for the group delay variation of the amplifier circuitry. The MMIC amplifier is capable of achieving a predicted constant group delay with little variation over a wide frequency range. In addition, the group delay equalizer circuit enables the amplifier to achieve flat (constant) gain over a wide bandwidth, while maintaining constant group delay. Furthermore, the group delay equalizer circuitry requires only a small portion of the total MMIC area.
Owner:REMEC DEFENSE & SPACE INC +1

Apparatus and methods for adaptive receiver delay equalization

Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters. Other embodiments and features are also disclosed.
Owner:ALTERA CORP

Automatic optical fiber transmission delay locking and equalization method

The invention discloses an automatic optical fiber transmission delay locking and equalization method applicable to optical fiber communication networks. Under the SDH (Synchronous Digital Hierarchy) system of conventional optical fiber transmission devices, by adding a zero-attenuation program-controllable optical fiber delay equalization network, in combination with an on-line optical fiber delay monitoring technique, the method reasonably chooses C mark and a time interval code Txk corresponding to C mark, a round trip comparison phase locking technique is utilized to separate out the change of an optical fiber delay value between a master station and a slave station in order to eliminate the adverse affection of the change of the optical fiber delay value on time and frequency synchronization, a three point-to-one point accurate measurement algorithm is adopted to constantly control the change of the optical fiber delay within an extremely narrow range, and thereby high-precision time and frequency synchronization is realized. The method provided by the invention is applied in combination with the on-line optical fiber delay monitoring technique, and can firmly control the delay change of optical fiber transmission within a range less than or equal to (1ns/day to 2ns/day to 5ns/day to 10ns/day).
Owner:四川泰富地面北斗科技股份有限公司

Four stage flow line digital signal processor and wireless on-chip system chip with same

The invention discloses a four stage flow line digital signal processor (DSP) and a wireless on-chip system chip with the same. The DSP adopts a four stage low power consumption flow line structure allowing delay equalization. The structure includes (1) an ADC quantization data write FIFO buffer process; (2) a ping-pong switch matrix read FIFO process; (3) wireless channel differential coding; (4) bit stream generation and transmission. The SOC can be configured into a transmitting or receiving mode through the DSP, and analog signals of front end OPA and BPF are selected by a multiplexer to transmit to an ADC for analog to digital conversion. The DSP and SOC chip flow mechanism is free of delayed bubbles and hazards and is convenient to expand; the flow line structure is low in power consumption, chip power consumption is reduced by the clock gating technique, and the subjective real-time evaluation is not affected by the multi-stage flow line.
Owner:INST OF ELECTRONICS CHINESE ACAD OF SCI

Method for carrying out equalization on 100M magnitude broadband reception signal

The invention provides a method for carrying out equalization on a 100M magnitude broadband reception signal, and is aimed at providing a method for using a simple time domain parallel structure to carry out time domain equalization on the broadband signal with small resource consumption, a fast operation speed, and no need of changing a transmission system. The method is realized through the following technical scheme: (1) employing a fraction interval adaptive blind equalization digital logic circuit with decision feedback, and receiving over-sampling baseband signal to be equalized in parallel; (2) carrying out addition of output of all transverse filtering structures as equalization output, and sending the baseband signal to be equalized into the transverse filtering structures in a forward direction equalization unit according to a corresponding phase relationship; (3) judging an equalization output result with a decision unit, and solving an error signal e(n) of the output result and a decision result; after e(n) is adjusted through an error convergence factor, carrying out gradient estimation and equalization coefficient updating, and sending an updated equalization coefficient to each transverse filtering structure to carry out an equalization operation. According to the method, contradiction between generating the equalization results and carrying out the equalization coefficient updating simultaneously in a code element is solved.
Owner:10TH RES INST OF CETC

SDN (Software Defined Network)-based multi-link delay equalization method and system

ActiveCN105791113AAvoid the disadvantage of not being able to choose the forwarding path with the least delayData switching networksCentralized computingMulti link
The embodiment of the invention provides an SDN-based multi-link delay equalization method and system. The method comprises the following steps that: an SDN switch transmits private two-layer message calculation link delay to a neighbor switch; the SDN switch reports MAC (Media Access Control) address information, port information and the link delay to an SDN controller in order that the SDN controller calculates network topology; and the SDN switch reports a message of an unmatched flow table to the SDN controller, wherein the message of the unmatched flow table includes destination MAC, the network topology and the link delay in order that the SDN controller calculates a forwarding path with smallest link delay and issues a flow table of the forwarding path with the smallest link delay to the SDN switch. Through adoption of the SDN-based multi-link delay equalization method and system, the forwarding path with the smallest delay can be selected accurately through centralized computing of the controller.
Owner:杭州吉吉知识产权运营有限公司

Navigation receiver radio frequency front end group delay characteristic equalization design method and device

ActiveCN113176592AGroup Delay EqualizationHigh frequency of fluctuationsSatellite radio beaconingTransmitter/receiver shaping networksEqualizationControl theory
The invention discloses a navigation receiver radio frequency front end group delay equalization design method and device. The method comprises the following steps: expanding a channel range in a frequency band by M%; measuring the time delay characteristic of the channel group in the expanded frequency band; obtaining denominator group delay of an all-pass filter; carrying out cos fitting on the denominator group time delay, and acquiring a denominator coefficient of the all-pass filter; obtaining a denominator polynomial coefficient; designing a first-stage all-pass filter; acquiring a balanced residual error, abandoning the extended frequency band, and designing a second-stage all-pass filter; and cascading the first-stage all-pass filter and the second-stage all-pass filter to obtain the group delay equalization all-pass filter. According to the invention, the all-pass filter of any group delay is designed by using a complex cepstrum theory, secondary equalization is performed according to the equalization residual error, and finally the group delay can be equalized by using the finite filter order in the specified passband so that the problem of a positioning error caused by related peak distortion brought by the group delay is solved.
Owner:NAT UNIV OF DEFENSE TECH
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