A calculation circuit, used to calculate and determine the sampling phase error signal of the feedback clock phase calibration circuit, has: a first delay unit chain, with a plurality of series-connected delay units, used to delay the digital estimation ak of the judgment device; the second delay unit chain, with a plurality of series-connected delay units for delaying the equalization signal (zk, ek); a multiplier array comprising a plurality of multipliers arranged in a matrix and estimating the undelayed numbers ak and the first delay unit chain The delay estimates of all delay units are multiplied by the equalization signal (zk, ek) and the delay output signals of all delay units of the second delay unit chain to produce a product signal; a weighting circuit multiplies the product signal produced by the multiplier array by an adjustable The weight coefficient (bi, j); and an adder, adding the product signal weighted by the weighting circuit to the sampling phase error signal (Vk) output by the signal output terminal of the calculation circuit.