Four stage flow line digital signal processor and wireless on-chip system chip with same

Abstract

The invention discloses a four stage flow line digital signal processor (DSP) and a wireless on-chip system chip with the same. The DSP adopts a four stage low power consumption flow line structure allowing delay equalization. The structure includes (1) an ADC quantization data write FIFO buffer process; (2) a ping-pong switch matrix read FIFO process; (3) wireless channel differential coding; (4) bit stream generation and transmission. The SOC can be configured into a transmitting or receiving mode through the DSP, and analog signals of front end OPA and BPF are selected by a multiplexer to transmit to an ADC for analog to digital conversion. The DSP and SOC chip flow mechanism is free of delayed bubbles and hazards and is convenient to expand; the flow line structure is low in power consumption, chip power consumption is reduced by the clock gating technique, and the subjective real-time evaluation is not affected by the multi-stage flow line.

Description

technical field [0001] The present invention relates to the field of integrated circuit system-on-chip (System-On-Chip, SOC) chips, and more particularly relates to a 4-stage pipeline digital signal processor (Digital Signal Processor, DSP) and a wireless SOC chip using the same. Background technique [0002] "Brain Health" is a major national 973 project, which is aimed at the prevention and diagnosis of depression, epilepsy and other mental diseases and symptoms, and finally realizes a portable wearable early warning and diagnosis service system with intelligent analysis of symptoms and the formation of cloud service brain big data System for behavioral statistics and research. The system intelligently interconnects the diagnosed person, mobile phone network, PC network, and patient location network through different levels of interfaces through wearable sensors. Among them, the physical layer circuit design of EEG sensor and circuit detection is the focus and difficulty ...

AI Technical Summary

Problems solved by technology

However, the patent application does not integrate the processor (Processor), analog-to-digital converter (ADC), radio frequency (RF) and other modules into the SOC chip

[0004] In addition, the Chinese utility model patent with the application number 201020283921.0 and the invention name "Electromagnetic Detection Device" discloses a wired method, which connects the data output by the sensor to the detection device through an anti-interference shielded cable, which has a high bit error rate and even The cable is not easy to carry and move; the application number is 201210032744.2, and the invention name is "a kind of EEG detection device and detection method". , ADC converters form multiple information streams, and gather them to the computer for analysis. The system is large and cannot realize wireless portable information transmission.

[0005] It can be seen that the various patent solutions in the prior art do not integrate all circuit IPs: amplifiers, analog-to-digital converters, digital IPs, and radio frequency IPs at the physical circuit layer, resulting in large product area, large power consumption, and Low integration, non-adjustable anti-interference and many other shortcomings

Due to the development of wearable devices, the trend of wearable EEG detection, long use time, light weight, small size, and multi-functional integration is becoming more and more obvious. Therefore, it is urgent to design a low-power EEG detection and processing device. SOC chip, pay attention to its low-noise and large-gain design of the interface with the sensor, to avoid many disadvantages caused by board-level multi-chips such as large area, heavy weight, large power consumption, and many board-level noise interference sources, and to facilitate future use of MEMS (micro- The electronic-machanical-system) process integrates the sensor with the back-end circuit (CMOS process)

Images