Calculating circuit for calculating sampling phase error

Abstract

A calculation circuit, used to calculate and determine the sampling phase error signal of the feedback clock phase calibration circuit, has: a first delay unit chain, with a plurality of series-connected delay units, used to delay the digital estimation ak of the judgment device; the second delay unit chain, with a plurality of series-connected delay units for delaying the equalization signal (zk, ek); a multiplier array comprising a plurality of multipliers arranged in a matrix and estimating the undelayed numbers ak and the first delay unit chain The delay estimates of all delay units are multiplied by the equalization signal (zk, ek) and the delay output signals of all delay units of the second delay unit chain to produce a product signal; a weighting circuit multiplies the product signal produced by the multiplier array by an adjustable The weight coefficient (bi, j); and an adder, adding the product signal weighted by the weighting circuit to the sampling phase error signal (Vk) output by the signal output terminal of the calculation circuit.

Description

Technical field [0001] The present invention relates to a calculation circuit for calculating the sampling phase error of the phase calibration circuit of the feedback clock. Background technique [0002] figure 1 Represents a data transmission system according to the prior art. Transceivers, or transmitters and receivers, receive signals sent from data sources, and transmit these analog transmitted signals to other transceivers through data transmission lines. The data transmission line is, for example, a twisted pair telephone line made of copper. In this case, the master clock is established at the transceiver of the COT (Central Office Terminal Equipment) at the exchange end. That is to say, the transmitted signal at the exchange end is sent synchronously with the clock signal of the transceiver. The transceiver of the RT at the user end forms a so-called slave clock, which means that the clock signal received at the receiving end is used as its transmit clock. [0003] Eve...

AI Technical Summary

Problems solved by technology

In the case of conventional clock phase calibration circuits according to the prior art, the calibration characteristics of the data transmission system for excess bandwidth in the sampling instant region are not approximately linear and therefore unstable

[0023] Also, in the case of conventional clock phase calibration circuits, the equalizer provided in the transceiver cannot prevent the occurrence of unstable calibration, as can be seen from FIG. 8

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